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features ? 80c52 compatible ? 8051 instruction compatible ? four 8-bit i/o ports (44 pins version) ? three 16-bit timer/counters ? 256 bytes scratch pad ram ? 11 interrupt sources with 4 priority levels ? isp (in-system programming) using standard v cc power supply ? integrated power monitor (por/pfd) to supervise internal power supply ? boot rom contains serial loader for in-system programming ? high-speed architecture ? in standard mode: 40 mhz (vcc 2.7v to 5.5v, both internal and external code execution) 60 mhz (vcc 4.5v to 5.5v and internal code execution only) ? in x2 mode (6 clocks/machine cycle) 20 mhz (vcc 2.7v to 5.5v, both internal and external code execution) 30 mhz (vcc 4.5v to 5.5v and internal code execution only) ? 128k bytes on-chip flash program/data memory ? 128 bytes page write with auto-erase ? 100k write cycles ? on-chip 8192 bytes expanded ram (xram) ? software selectable size (0, 256, 512, 768, 1024, 1792, 2048, 4096, 8192 bytes) ? dual data pointer ? extended stack pointer to 512 bytes ? variable length movx for slow ram/peripherals ? improved x2 mode with independant selection for cpu and each peripheral ? keyboard interrupt interface on port 1 ? spi interface (master/slave mode) ? 8-bit clock prescaler ? programmable counter array with: ? high speed output ?compare/capture ? pulse width modulator ? watchdog timer capabilities ? asynchronous port reset ? two full duplex enhanced uart with dedicated internal baud rate generator ? low emi (inhibit ale) ? hardware watchdog timer (one-time enabled with reset-out), power-off flag ? power control modes: idle mode, power-down mode ? power supply: 2.7v to 5.5v ? temperature ranges: industrial (-40 to +85 c) ? packages: plcc44, vqfp44 8-bit flash microcontroller at89c51re2
2 7663e?8051?10/08 at89c51re2 description at89c51re2 is a high performance cmos flash version of the 80c51 cmos single chip 8-bit microcontroller. it contains a 128 kbytes flash memory block for program. the 128 kbytes flash memory can be programmed either in parallel mode or in serial mode with the isp capability or with software. the programming voltage is internally generated from the standard v cc pin. the at89c51re2 retains all features of the atmel 80c52 with 256 bytes of internal ram, a 10- source 4-level interrupt controller and three timer/counters. in addition, the at89c51re2 has a programmabl e counter array, an xram of 8192 bytes, a hardware watchdog timer, spi and keyboard, two serial channels that facilitates multiproces- sor communication (euart), a speed improvement mechanism (x2 mode) and an extended stack mode that allows the stack to be extended in the lower 256 bytes of xram. the fully static design of the at89c51re2 allows to reduce system power consumption by bringing the clock frequency down to any value, even dc, without loss of data. the at89c51re2 has 2 software-selectable modes of reduced activity and 8-bit clock prescaler for further reduction in power consumption. in the idle mode the cpu is frozen while the periph- erals and the interrupt system are still operating. in the power-down mode the ram is saved and all other functions are inoperative. the added features of the at89c51re2 make it more powerful for applications that need pulse width modulation, high speed i/o and counting capabilities such as alarms, motor control, corded phones, smart card readers. table 1. memory size and i/o pins at89c51re2 flash (bytes) xram (bytes) total ram (bytes) i/o plcc44 vqfp44 128k 8192 8192 + 256 34
3 7663e?8051?10/08 at89c51re2 block diagram figure 1. block diagram timer 0 int ram 256x8 t0 t1 rxd_0 txd_0 wr rd ea psen ale/ xtala2 xtala1 euart cpu timer 1 int1 ctrl int0 (2) (2) c51 core (2) (2) (2) (2) port 0 p0 port 1 port 2 port 3 p1 p2 p3 xram 8192 x 8 ib-bus pca reset prog watch dog pca eci vss vcc (2) (2) (1) (1): alternate function of port 1 (2): alternate function of port 3 (1) timer2 t2ex t2 (1) (1) flash 128kx8 keyboard (1) keyboard miso mosi sck ss (3): alternate function of port 6 (3) (3) port4 p4 (1) (1) (1) (1) boot 4k x8 rom regulator por / pfd port 5 p5 parallel i/o ports & external bus spi por pfd xtalb2 xtalb1(1) euart_1 rxd_1 txd_1 twi sda scl
4 7663e?8051?10/08 at89c51re2 pin configurations 43 42 41 40 39 44 38 37 36 35 34 p1.4/cex1 p1.0/t2/xtalb1 p1.1/t2ex/ss p1.3/cex0 p1.2/eci rx_ocd vcc p0.0/ad0 p0.2/ad2 p0.3/ad3 p0.1/ad1 p0.4/ad4 p0.6/ad6 p0.5/ad5 p0.7/ad7 ale psen ea p6.1/txd_1/scl p2.7/a15 p2.5/a13 p2.6/a14 p1.5/cex2/miso p1.6/cex3/sck p1.7/cex4/mosi rst p3.0/rxd_0 p6.0/rxd_1/sda p3.1/txd_0 p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1 p3.6/wr p3.7/rd xtal2 xtal1 vss p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 tx_ocd 12 13 17 16 15 14 20 19 18 21 22 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 vqfp44 plcc44 at89c51re2 at89c51re2 18 19 23 22 21 20 26 25 24 27 28 5 4 3 2 1 6 44 43 42 41 40 p1.4/cex1 p1.0/t2 p1.1/t2ex/ss p1.3/cex0 p1.2/eci rx_ocd vcc p0.0/ad0 p0.2/ad2 p0.1/ad1 p0.4/ad4 p0.6/ad6 p0.5/ad5 p0.7/ad7 ale psen ea p6.1/txd_1/scl p2.7/a15 p2.5/a13 p2.6/a14 p3.6/wr p3.7/rd xtal2 xtal1 vss p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 p1.5/cex2/miso p1.6/cex3/sck p1.7/cex4/mosi rst p3.0/rxd_0 p6.0/rxd_1/sda p3.1/txd_0 p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1 p0.3/ad3 tx_ocd 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29
5 7663e?8051?10/08 at89c51re2 table 2. pin description mnemonic pin number type name and function lcc vqfp 1.4 v ss 22 16 i ground: 0v reference vss1 39 i optional ground: contact the sales office for ground connection. v cc 44 38 i power supply: this is the power supply voltage for normal, idle and power-down operation p0.0-p0.7 43-36 37-30 i/o port 0 : port 0 is an open-drain, bidirectional i/o port. port 0 pins that have 1s written to them float and can be used as high impedance inputs. port 0 must be polarized to v cc or v ss in order to prevent any parasitic current consumpti on. port 0 is also the multiplexed low-order address and data bus during access to external program and data memory. in this application, it uses strong internal pull-up when emitting 1s. port 0 also inputs the code bytes during eprom programming. external pull-up s are required during program verification during which p0 outputs the code bytes. p1.0-p1.7 2-9 40-44 1-3 i/o port 1: port 1 is an 8-bit bidirectional i/o port with internal pull-ups. port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 1 pins that are externally pulled low will s ource current because of the internal pull-ups. port 1 also receives the low-order address byte during memory programming and verification. alternate functions for tsc8x54/58 port 1 include: 240i/o t2 (p1.0): timer/counter 2 external count input/clockout 341 i t2ex (p1.1): timer/counter 2 reload/capture/direction control 442 i eci (p1.2): external clock for the pca 543i/o cex0 (p1.3): capture/compare external i/o for pca module 0 644i/o cex1 (p1.4): capture/compare external i/o for pca module 1 71i/o cex2 (p1.5): capture/compare external i/o for pca module 2 82i/o cex3 (p1.6): capture/compare external i/o for pca module 3 93i/o cex4 (p1.7): capture/compare external i/o for pca module 4 p2.0-p2.7 24-31 18-25 i/o port 2 : port 2 is an 8-bit bidirectional i/o port with internal pull-ups. port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 2 pins that are externally pulled low will s ource current because of the internal pull-ups. port 2 emits the high-order address byte duri ng fetches from exter nal program memory and during accesses to external data memory that use 16-bit addresses (movx @dptr).in this application, it uses strong internal pull-ups em itting 1s. during accesses to external data memory that use 8-bit addresses (movx @ri), port 2 emits the contents of the p2 sfr. some port 2 pins receive the high order address bits during eprom programming and verification: p2.0 to p2.5 for rb devices p2.0 to p2.6 for rc devices p2.0 to p2.7 for rd devices. p3.0-p3.7 11, 13-19 5, 7-13 i/o port 3: port 3 is an 8-bit bidirectional i/o port with internal pull-ups. port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 3 pins that are externally pulled low will s ource current because of the internal pull-ups. port 3 also serves the special features of the 80c51 family, as listed below. 11 5 i rxd_0 (p3.0): serial input port 13 7 o txd_0 (p3.1): serial output port 14 8 i int0 (p3.2): external interrupt 0
6 7663e?8051?10/08 at89c51re2 15 9 i int1 (p3.3): external interrupt 1 16 10 i t0 (p3.4): timer 0 external input 17 11 i t1 (p3.5): timer 1 external input 18 12 o wr (p3.6): external data memory write strobe 19 13 o rd (p3.7): external data memory read strobe p6.0-p6.1 12,34 6, 28 port 6: port 6 is an 2-bit bidirectional i/o port with internal pull-ups. port 6 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 6 pins that are externally pulled low will s ource current because of the internal pull-ups. port 6 also serves some special features as listed below. 12 6 i rxd_1 (p6.0): serial input port 12 6 i/o sda (p6.0) : twi serial data sda is the bidirectional twi data line. 34 28 o txd_1 (p6.1) : serial output port 34 28 i/o scl ( p6.1) : twi serial clock scl output the serial clock to slave peripherals. scl input the serial clock from master. reset 10 4 i/o reset: a high on this pin for two machine cycles while the oscillator is running, resets the device. an internal diffused resistor to v ss permits a power-on reset using only an external capacitor to v cc . this pin is an output when the hardware watchdog forces a system reset. ale/prog 33 27 o (i) address latch enable/program pulse: output pulse for latching the low byte of the address during an access to external memory. in normal operation, ale is emitted at a constant rate of 1/6 (1/3 in x2 mode) t he oscillator frequency, and can be used for external timing or clocking. note that one ale pulse is skipped during each access to external data memory. this pin is also the program pulse input (prog ) during flash programming. ale can be disabled by setting sfr?s auxr.0 bit. with this bit set, ale will be inactive during internal fetches. psen 32 26 o program store enable: the read strobe to external program memory. when executing code from the external program memory, psen is activated twice each machine cycle, except that two psen activations are skipped during each access to external data memory. psen is not activated during fetches from internal program memory. ea 35 29 i external access enable: ea must be externally held low to enable the device to fetch code from external program memory locations 0000h to ffffh (rd). if security level 1 is programmed, ea will be internally latched on reset. xtal1 21 15 i crystal 1: input to the inverting oscillator amplifier and input to the internal clock generator circuits. xtal2 20 14 o crystal 2: output from the inverting oscillator amplifier tx_ocd 23 17 o tx_ocd: on chip debug serial output port rx_ocd 1 39 i rx_ocd: on chip debug serial input port mnemonic pin number type name and function lcc vqfp 1.4
7 7663e?8051?10/08 at89c51re2 sfr mapping the special function registers (sfrs) of the at89c51re2 fall into the following categories: ? c51 core registers: acc, b, dph, dpl, psw, sp ? i/o port registers: p0, p1, p2, p3, p4, p5, p6 ? timer registers: t2con, t2mod, tcon, th0, th1, th2, tmod, tl0, tl1, tl2, rcap2l, rcap2h ? serial i/o port registers: saddr_0, saden_0, sbuf_0, scon_0, saddr_1, saden_1, sbuf_1, scon_1, ? pca (programmable counter array) registers: ccon, ccapmx, cl, ch, ccapxh, ccapxl (x: 0 to 4) ? power and clock control registers: pcon, ckal, ckcon0_1 ? hardware watchdog timer registers: wdtrst, wdtprg ? interrupt system registers: ie0, ipl0, iph0, ie1, ipl1, iph1 ? keyboard interface registers: kbe, kbf, kbls ? 2-wire interface registers: sscon, sscs, ssdat, ssadr ? spi registers: spcon, spstr, spdat ? brg (baud rate generator) registers: brl_0, brl_1, bdrcon_0, bdrcon_1 ? memory register: fcon, fsta ? clock prescaler register: ckrl ? others: auxr, auxr1, ckcon0, ckcon1, bmsel
8 7663e?8051?10/08 at89c51re2 table 3. c51 core sfrs mnemonicaddname 76543210 acc e0h accumulator b f0h b register psw d0h program status word cy ac f0 rs1 rs0 ov f1 p sp 81h stack pointer dpl 82h data pointer low byte dph 83h data pointer high byte table 4. system management sfrs mnemonicaddname 76543210 pcon 87h power control smod1_0 smod0_0 - pof gf1 gf0 pd idl auxr 8eh auxiliary register 0 - - m0 xrs2 xrs1 xrs0 extra m ao auxr1 a2h auxiliary register 1 ees sp9 u2 - gf2 0 - dps ckrl 97hclock reload register -------- bmsel 92h bank memory select mbo2 mbo1 mbo0 - fbs2 fbs1 fbs0 ckcon0 8fh clock control register 0 twix2 wdx2 pcax2 six2_0 t2x2 t1x2 t0x2 x2 ckcon1afhclock control register 1 ------six2_1spix2 table 5. interrupt sfrs mnemonicaddname 76543210 ien0 a8h interrupt enable control 0 ea ec et2 es et1 ex1 et0 ex0 ien1 b1hinterrupt enable control 1 ----es_1espietwiekbd iph0 b7h interrupt priority control high 0 - ppch pt2h psh pt1h px1h pt0h px0h ipl0 b8h interrupt priority control low 0 - ppcl pt2l psl pt1l px1l pt0l px0l iph1 b3hinterrupt priority control high 1----psh_1spihie2chkbdh ipl1 b2hinterrupt priority control low 1----psl_1spilie2clkbdl table 6. port sfrs mnemonicaddname 76543210 p0 80h 8-bit port 0 p1 90h 8-bit port 1 p2 a0h 8-bit port 2 p3 b0h 8-bit port 3 p4 c0h 8-bit port 4
9 7663e?8051?10/08 at89c51re2 p5 e8h 8-bit port 5 p6 f8h2-bit port 5 ------ table 6. port sfrs mnemonicaddname 76543210 table 7. flash and eeprom data memory sfr mnemonicaddname 76543210 fcon d1h flash controller control fpl3 fpl2 fpl1 fpl0 fps fmod2 fmod1 fmod0 fsta d3h flash controller status fmr fse fload fbusy table 8. timer sfrs mnemonicaddname 76543210 tcon 88h timer/counter 0 and 1 control tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 tmod 89h timer/counter 0 and 1 modes gate1 c/t1# m11 m01 gate0 c/t0# m10 m00 tl0 8ah timer/counter 0 low byte th0 8ch timer/counter 0 high byte tl1 8bh timer/counter 1 low byte th1 8dh timer/counter 1 high byte wdtrst a6h watchdog timer reset wdtprga7hwatchdog timer program -----wto2wto1wto0 t2con c8h timer/counter 2 control tf2 exf2 rclk tclk exen2 tr2 c/t2# cp/rl2# t2mod c9h timer/counter 2 mode ------t2oedcen rcap2h cbh timer/counter 2 reload/capture high byte rcap2l cah timer/counter 2 reload/capture low byte th2 cdh timer/counter 2 high byte tl2 cch timer/counter 2 low byte table 9. pca sfrs mnemo -nicaddname 76543210 ccon d8h pca timer/counter control cf cr - ccf4 ccf3 ccf2 ccf1 ccf0 cmod d9h pca timer/counter mode cidl wdte - - - cps1 cps0 ecf cl e9h pca timer/counter low byte
10 7663e?8051?10/08 at89c51re2 ch f9h pca timer/counter high byte ccapm0 ccapm1 ccapm2 ccapm3 ccapm4 dah dbh dch ddh deh pca timer/counter mode 0 pca timer/counter mode 1 pca timer/counter mode 2 pca timer/counter mode 3 pca timer/counter mode 4 - ecom0 ecom1 ecom2 ecom3 ecom4 capp0 capp1 capp2 capp3 capp4 capn0 capn1 capn2 capn3 capn4 mat0 mat1 mat2 mat3 mat4 tog0 tog1 tog2 tog3 tog4 pwm0 pwm1 pwm2 pwm3 pwm4 eccf0 eccf1 eccf2 eccf3 eccf4 ccap0h ccap1h ccap2h ccap3h ccap4h fah fbh fch fdh feh pca compare capture module 0 h pca compare capture module 1 h pca compare capture module 2 h pca compare capture module 3 h pca compare capture module 4 h ccap0h7 ccap1h7 ccap2h7 ccap3h7 ccap4h7 ccap0h6 ccap1h6 ccap2h6 ccap3h6 ccap4h6 ccap0h5 ccap1h5 ccap2h5 ccap3h5 ccap4h5 ccap0h4 ccap1h4 ccap2h4 ccap3h4 ccap4h4 ccap0h3 ccap1h3 ccap2h3 ccap3h3 ccap4h3 ccap0h2 ccap1h2 ccap2h2 ccap3h2 ccap4h2 ccap0h1 ccap1h1 ccap2h1 ccap3h1 ccap4h1 ccap0h0 ccap1h0 ccap2h0 ccap3h0 ccap4h0 ccap0l ccap1l ccap2l ccap3l ccap4l eah ebh ech edh eeh pca compare capture module 0 l pca compare capture module 1 l pca compare capture module 2 l pca compare capture module 3 l pca compare capture module 4 l ccap0l7 ccap1l7 ccap2l7 ccap3l7 ccap4l7 ccap0l6 ccap1l6 ccap2l6 ccap3l6 ccap4l6 ccap0l5 ccap1l5 ccap2l5 ccap3l5 ccap4l5 ccap0l4 ccap1l4 ccap2l4 ccap3l4 ccap4l4 ccap0l3 ccap1l3 ccap2l3 ccap3l3 ccap4l3 ccap0l2 ccap1l2 ccap2l2 ccap3l2 ccap4l2 ccap0l1 ccap1l1 ccap2l1 ccap3l1 ccap4l1 ccap0l0 ccap1l0 ccap2l0 ccap3l0 ccap4l0 table 10. serial i/o port sfrs mnemonicaddname 7 6 543210 scon_0 98h serial control 0 fe/sm0_0 sm1_0 sm2_0 ren_0 tb8_0 rb8_0 ti_0 ri_0 sbuf_0 99h serial data buffer 0 saden_0 b9h slave address mask 0 saddr_0 a9h slave address 0 bdrcon_0 9bh baud rate control 0 brr_0 tbck_0 rbck_0 spd_0 src_0 brl_0 9ah baud rate reload 0 scon_1 c0h serial control 1 fe_1/sm0_1 sm1_1 sm2_1 ren_1 tb8_1 rb8_1 ti_1 ri_1 sbuf_1 c1h serial data buffer 1 saden_1 bah slave address mask 1 saddr_1 aah slave address 1 bdrcon_1 bch baud rate control 1 smod1_1 smod0_1 brr_1 tbck_1 rbck_1 spd_1 src_1 brl_1 bbh baud rate reload 1 table 9. pca sfrs (continued) mnemo -nicaddname 76543210
11 7663e?8051?10/08 at89c51re2 table 11. spi controller sfrs mnemonicaddname 76543210 spcon c3h spi control spr2 spen ssdis mstr cpol cpha spr1 spr0 spscr c4h spi status spif ovr modf spte uartm spteie modfie spdat c5h spi data spd7 spd6 spd5 spd4 spd3 spd2 spd1 spd0 table 12. two-wire interface controller sfrs mnemonic add name 7 6 5 4 3 2 1 0 sscon 93h synchronous serial control sscr2 sspe sssta sssto ssi ssaa sscr1 sscr0 sscs 94h synchronous serial status ssc4 ssc3 ssc2 ssc1 ssc0 0 0 0 ssdat 95h synchronous serial data ssd7 ssd6 ssd5 ssd4 ssd3 ssd2 ssd1 ssd0 ssadr 96h synchronous serial address ssa7 ssa6 ssa5 ssa4 ssa3 ssa2 ssa1 ssgc table 13. keyboard interface sfrs mnemonicaddname 76543210 kbls 9ch keyboard level selector kbls7 kbls6 kbls5 kbls4 kbls3 kbls2 kbls1 kbls0 kbe 9dh keyboard input enable kbe7 kbe6 kbe5 kbe4 kbe3 kbe2 kbe1 kbe0 kbf 9eh keyboard flag register kbf7 kbf6 kbf5 kbf4 kbf3 kbf2 kbf1 kbf0
12 7663e?8051?10/08 at89c51re2 table below shows all sfrs with their address and their reset value. table 14. sfr mapping bit addressable non bit addressable 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f f8h p6 xxxx xx11 ch 0000 0000 ccap0h xxxx xxxx ccap1h xxxx xxxx ccap2h xxxx xxxx ccap3h xxxx xxxx ccap4h xxxx xxxx ffh f0h b 0000 0000 f7h e8h p5 1111 1111 cl 0000 0000 ccap0l xxxx xxxx ccap1l xxxx xxxx ccap2l xxxx xxxx ccap3l xxxx xxxx ccap4l xxxx xxxx efh e0h acc 0000 0000 e7h d8h ccon 00x0 0000 cmod 00xx x000 ccapm0 x000 0000 ccapm1 x000 0000 ccapm2 x000 0000 ccapm3 x000 0000 ccapm4 x000 0000 dfh d0h psw 0000 0000 fcon 0000 0000 fsta xxxx x000 d7h c8h t2con 0000 0000 t2mod xxxx xx00 rcap2l 0000 0000 rcap2h 0000 0000 tl2 0000 0000 th2 0000 0000 cfh c0h u2(auxr1.5) =0 scon_1 0000 0000 sbuf_1 0000 0000 spcon 0001 0100 spscr 0000 0000 spdat xxxx xxxx c7h u2(auxr1.5) =1 p4 1111 1111 b8h ipl0 x000 000 saden_0 0000 0000 saden1 0000 0000 brl_1 0000 0000 bdrcon_1 xxx0 0000 bfh b0h p3 1111 1111 ien1 xxxx 0000 ipl1 xxxx 0000 iph1 xxxx 0111 iph0 x000 0000 b7h a8h ien0 0000 0000 saddr_0 0000 0000 saddr_1 0000 0000 ckcon1 xxxx xx00 afh a0h p2 1111 1111 auxr1 000x 11x0 wdtrst xxxx xxxx wdtprg xxxx x000 a7h 98h scon_0 0000 0000 sbuf_0 xxxx xxxx brl_0 0000 0000 bdrcon_0 xxx0 0000 kbls 0000 0000 kbe 0000 0000 kbf 0000 0000 9fh 90h p1 1111 1111 bmsel 0000 0yyy sscon 0000 0000 sscs 1111 1000 ssdat 1111 1111 ssadr 1111 1110 ckrl 1111 1111 97h 88h tcon 0000 0000 tmod 0000 0000 tl0 0000 0000 tl1 0000 0000 th0 0000 0000 th1 0000 0000 auxr xx00 1000 ckcon0 0000 0000 8fh 80h p0 1111 1111 sp 0000 0111 dpl 0000 0000 dph 0000 0000 pcon 00x1 0000 87h 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f reserved
13 7663e?8051?10/08 at89c51re2 enhanced features in comparison to the original 80c52, the at89c51re2 implements some new features, which are : ? x2 option ? dual data pointer ? extended ram ? extended stack ? programmable counter array (pca) ? hardware watchdog ? spi interface ? 4-level interrupt priority system ? power-off flag ? once mode ? ale disabling ? enhanced features on the uart and the timer 2 x2 feature the at89c51re2 core needs only 6 clock periods per machine cycle. this feature called ?x2? provides the following advantages: ? divide frequency crystals by 2 (cheaper crystals) while keeping same cpu power. ? save power consumption while keeping same cpu power (oscillator power saving). ? save power consumption by dividing dynamically the operating frequency by 2 in operating and idle modes. ? increase cpu power by 2 while keeping same crystal frequency. in order to keep the original c51 compatibility, a divider by 2 is inserted between the xtal1 sig- nal and the main clock input of the core (phase generator). this divider may be disabled by software. description the clock for the whole circuit and peripherals is first divided by two before being used by the cpu core and the peripherals. this allows any cyclic ratio to be accepted on xtal1 input. in x2 mode, as this divider is bypassed, the signals on xtal1 must have a cyclic ratio between 40 to 60%. figure 2 shows the clock generation block diagram. x2 bit is validated on the rising edge of the xtal1 2 to avoid glitches when switching from x2 to std mode. figure 3 shows the switching mode waveforms. figure 2. clock generation diagram xtal1 2 ckcon0 x2 8 bit prescaler f osc fxtal 0 1 xtal1:2 f clk cpu f clk periph ckrl
14 7663e?8051?10/08 at89c51re2 figure 3. mode switching waveforms the x2 bit in the ckcon0 register (see table 15) allows a switch from 12 clock periods per instruction to 6 clock periods and vice versa. at reset, the speed is set according to x2 bit of the fuse configuration byte (fcb). by default, standard mode is active. setting the x2 bit activates the x2 feature (x2 mode). the t0x2, t1x2, t2x2, uartx2, pcax2, and wdx2 bits in the ckcon0 register (see table 15.) and spix2 bit in the ckcon1 register (see table 16) allows a switch from standard peripheral speed (12 clock periods per peripheral clock cycle) to fast peripheral speed (6 clock periods per peripheral clock cycle). these bits are active only in x2 mode. xtal1:2 xtal1 cpu clock x2 bit x2 mode std mode std mode f osc
15 7663e?8051?10/08 at89c51re2 table 15. ckcon0 register ckcon0 - clock control register (8fh) reset value = x000 000?hsb. x2?b (see ?fuse configuration byte: fcb?) not bit addressable 76543210 twix2 wdx2 pcax2 six2_0 t2x2 t1x2 t0x2 x2 bit number bit mnemonic description 7twix2 2-wire clotbck (this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect) cleared to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 6wdx2 watchdog clock (this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect). cleared to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 5pcax2 programmable counter array clock (this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect). cleared to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 4 six2_0 enhanced uart0 clock (mode 0 and 2) (this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect). cleared to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 3t2x2 timer2 clock (this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect). cleared to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 2t1x2 timer1 clock (this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect). cleared to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 1t0x2 timer0 clock (this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect). cleared to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 0x2 cpu clock cleared to select 12 clock periods per machine cycle (std mode) for cpu and all the peripherals. set to select 6clock periods per machine cycle (x2 mode) and to enable the individual peripherals?x2? bits. programm ed by hardware after power-up regarding hardware security byte (hsb), default setting, x2 is cleared.
16 7663e?8051?10/08 at89c51re2
17 7663e?8051?10/08 at89c51re2 table 16. ckcon1 register ckcon1 - clock control register (afh) reset value = xxxx xx00b not bit addressable 76543210 ------six2_1spix2 bit number bit mnemonic description 7- reserved 6- reserved 5- reserved 4- reserved 3- reserved 2- reserved 1 six2_1 enhanced uart1 clock (mode 0 and 2) (this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect). cleared to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 0 spix2 spi (this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect). clear to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle.
18 7663e?8051?10/08 at89c51re2 dual data pointer register dptr the additional data pointer can be used to speed up code execution and reduce code size. the dual dptr structure is a way by which the chip will specify the address of an external data memory location. there are two 16-bit dptr registers that address the external memory, and a single bit called dps = auxr1.0 (see table 17) that allows the program code to switch between them (refer to figure 4). figure 4. use of dual pointer external data memory auxr1(a2h) dps dph(83h) dpl(82h) 0 7 dptr0 dptr1
19 7663e?8051?10/08 at89c51re2 table 17. auxr1 register auxr1- auxiliary register 1(0a2h) reset value: xx0x xx0x0b not bit addressable note: *bit 2 stuck at 0; this allows to use inc auxr1 to toggle dps without changing gf3. assembly language ; block move using dual data pointers ; modifies dptr0, dptr1, a and psw ; note: dps exits opposite of entry state ; unless an extra inc auxr1 is added ; 00a2 auxr1 equ 0a2h ; 0000 909000mov dptr,#source ; address of source 0003 05a2 inc auxr1 ; switch data pointers 0005 90a000 mov dptr,#dest ; address of dest 0008 loop: 0008 05a2 inc auxr1 ; switch data pointers 000a e0 movx a,@dptr ; get a byte from source 000b a3 inc dptr ; increment source address 000c 05a2 inc auxr1 ; switch data pointers 000e f0 movx @dptr,a ; write the byte to dest 000f a3 inc dptr ; increment dest address 76543210 ees sp9 u2 - gf2 0 - dps bit number bit mnemonic description 7ees enable extended stack this bit allows the selection of the stack extended mode. set to enable the extended stack clear to disable the extended stack (default value) 6sp9 stack pointer 9th bit this bit has no effect when the ees bit is cleared. set when the stack pointer belongs to the xram memory space cleared when the stack pointer belongs to the 256bytes of internal ram. 5u2 p4 bit addressable clear to map scon_1 register at c0h sfr address set to map p4 port register at c0h address. 4- reserved the value read from this bit is indeterminate. do not set this bit. 3gf2 this bit is a general purpose user flag. * 20 always cleared. 1- reserved the value read from this bit is indeterminate. do not set this bit. 0dps data pointer selection cleared to select dptr0. set to select dptr1.
20 7663e?8051?10/08 at89c51re2 0010 70f6jnz loop ; check for 0 terminator 0012 05a2 inc auxr1 ; (optional) restore dps inc is a short (2 bytes) and fast (12 clocks) way to manipulate the dps bit in the auxr1 sfr. however, note that the inc instruction does not directly force the dps bit to a particular state, but simply toggles it. in simple routines, such as the block move example, only the fact that dps is toggled in the proper sequence matters, not it s actual value. in other words, the block move routine works the same whether dps is '0' or '1' on entry. observe that without the last instruc- tion (inc auxr1), the routine will exit with dps in the opposite state.
21 7663e?8051?10/08 at89c51re2 memory architecture at89c51re2 features several on-chip memories: ? flash memory: containing 128 kbytes of program memory (user space) organized into 128 bytes pages. ?boot rom: 4k bytes for boot loader. ? 8k bytes internal xram physical memory organisation figure 5. physical memory organisation 128k bytes flash memory fm0 hardware security (1 byte) column latches (128 bytes) user space 4k bytes rom 1ffffh 00000h rm0 fuse configuration byte(1 byte) fcb hsb 256 bytes iram xram 8k bytes
22 7663e?8051?10/08 at89c51re2 expanded ram (xram) the at89c51re2 provides additional bytes of random access memory (ram) space for increased data parameter handling and high level language usage. at89c51re2 devices have expanded ram in external data space configurable up to 8192bytes (see table 18.). the at89c51re2 has internal data memory that is mapped into four separate segments. the four segments are: 1. the lower 128 bytes of ram (addresses 00h to 7fh) are directly and indirectly addressable. 2. the upper 128 bytes of ram (addresses 80h to ffh) are indirectly addressable only. 3. the special function registers, sfrs, (addresses 80h to ffh) are directly addressable only. 4. the expanded ram bytes are indirectly accessed by movx instructions, and with the extram bit cleared in the auxr register (see table 18). the lower 128 bytes can be accessed by either direct or indirect addressing. the upper 128 bytes can be accessed by indirect addressing only. the upper 128 bytes occupy the same address space as the sfr. that means they have the same address, but are physically sepa- rate from sfr space. figure 6. internal and external data memory address when an instruction accesses an internal location above address 7fh, the cpu knows whether the access is to the upper 128 bytes of data ram or to sfr space by the addressing mode used in the instruction. ? instructions that use direct addressing access sfr space. for example: mov 0a0h, # data, accesses the sfr at location 0a0h (which is p2). ? instructions that use indirect addressing access the upper 128 bytes of data ram. for example: mov @r0, # data where r0 contains 0a0h, accesses the data byte at address 0a0h, rather than p2 (whose address is 0a0h). ? the xram bytes can be accessed by indirect addressing, with extram bit cleared and movx instructions. this part of memory which is physically located on-chip, logically occupies the first bytes of external data memory. the bits xrs0 and xrs1 are used to hide a part of the available xram as explained in table 18. this can be useful if external peripherals are mapped at addresses already used by the internal xram. xram upper 128 bytes internal ram lower 128 bytes internal ram special function register 80h 80h 00 0ffh to 1fffh 0ffh 00 0ffh external data memory 0000 00ffh up to 1fffh 0ffffh indirect accesses direct accesses direct or indirect accesses 7fh
23 7663e?8051?10/08 at89c51re2 ? with extram = 0, the xram is indirectly addressed, using the movx instruction in combination with any of the registers r0, r1 of the selected bank or dptr. an access to xram will not affect ports p0, p2, p3.6 (wr) and p3.7 (rd). for example, with extram = 0, movx @r0, # data where r0 contains 0a0h, accesses the xram at address 0a0h rather than external memory. an access to external data memory locations higher than the accessible size of the xram will be performed with the movx dptr instructions in the same way as in the standard 80c51, with p0 and p2 as data/address busses, and p3.6 and p3.7 as write and read timing signals. accesses to xram above 0ffh can only be done by the use of dptr. ? with extram = 1 , movx @ri and movx @dptr will be similar to the standard 80c51.movx @ ri will provide an eight-bit address multiplexed with data on port0 and any output port pins can be used to output higher order address bits. this is to provide the external paging capability. movx @dptr will generate a sixteen-bit address. port2 outputs the high-order eight address bits (the contents of dph) while port0 multiplexes the low-order eight address bits (dpl) with data. movx @ ri and movx @dptr will generate either read or write signals on p3.6 (wr ) and p3.7 (rd ). the stack pointer (sp) may be located anywhere in the 256 bytes ram (lower and upper ram) internal data memory. the stack may be located in the 256 lower bytes of the xram by activat- ing the extended stack mode (see ees bit in auxr1). the m0 bit allows to stretch the xram timings; if m0 is set, the read and write pulses are extended from 6 to 30 clock periods. this is useful to access external slow peripherals.
24 7663e?8051?10/08 at89c51re2 registers table 18. auxr register auxr - auxiliary register (8eh) reset value = xx01 1100b not bit addressable 76543210 - - m0 xrs2 xrs1 xrs0 extram ao bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6- reserved the value read from this bit is indeterminate. do not set this bit. 5m0 pulse length cleared to stretch movx control: the rd/ and the wr/ pulse length is 6 clock periods (default). set to stretch movx control: the rd/ and the wr/ pulse length is 30 clock periods. 4-2 xrs2:0 xram size xrs2 xrs1 xrs0 xram size 0 0 0 256 bytes 0 0 1 512 bytes 0 1 0 768 bytes 0 1 1 1024 bytes 1 0 0 1792 bytes 1 0 1 2048 bytes 1 1 0 4096 bytes 1 1 1 8192 bytes (default) 1extram extram bit cleared to access internal xram using movx @ ri/ @ dptr. set to access external memory. programmed by hardware afte r power-up regarding hardware security byte (hsb), default setting, xram selected. 0ao ale output bit cleared, ale is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if x2 mode is used). (default) set, ale is active only during a movx or movc instruction is used.
25 7663e?8051?10/08 at89c51re2 extended stack the lowest bytes of the xram may be used to allow extension of the stack pointer. the extended stack allows to extend the standard c51 stack over the 256 bytes of internal ram. when the extended stack mode is activated (ees bit in auxr1), the stack pointer (sp) can grow in the lower 256 bytes of the xram area. the stack extension consists in a 9 bits stack pointer where the ninth bit is located in sp9 (bit 6 of auxr1). the sp9 then indicates if the st ack pointer belongs to the internal ram (sp9 cleared) or to the xram memory (sp9 set). to ensure backward compatibility with standard c51 architecture, the extended mode is disable at chip reset. figure 7. stack modes figure 8. auxr1 register auxr1- auxiliary register 1(0a2h) 00h ffh 0000h ffffh 256 bytes iram 00h ffh logical mcu address 256 sp values rollover within 256b of iram 00h ffh 0000h 256 bytes iram 00h ffh 512 sp values rollover in: 00ffh 00h ffh 256b of iram + lower 256b of xram xram sp value ffffh logical mcu address xram sp value standard c51 stack mode ees = 0 extended stack mode stack ees = 1 sp9=1 sp9=0 76543210 ees sp9 u2 - gf2 0 - dps bit number bit mnemonic description 7ees enable extended stack this bit allows the selection of the stack extended mode. set to enable the extended stack clear to disable the extended stack (default value)
26 7663e?8051?10/08 at89c51re2 reset value = 00xx 00x0b not bit addressable 6sp9 stack pointer 9th bit this bit has no effect when the ees bit is cleared. set when the stack pointer belongs to the xram memory space cleared when the stack pointer belongs to the 256bytes of internal ram. set and cleared by hardware. can only be read. 5u2 p4 bit addressable clear to map scon_1 register at c0h sfr address set to map p4 port register at c0h address. 4- reserved the value read from this bit is indeterminate. do not set this bit. 3gf2 this bit is a general purpose user flag. * 20 always cleared. 1- reserved the value read from this bit is indeterminate. do not set this bit. 0dps data pointer selection cleared to select dptr0. set to select dptr1. bit number bit mnemonic description
27 7663e?8051?10/08 at89c51re2 flash memory general description the flash memory increases eprom and rom functionality with in-circuit electrical erasure and programming. it contains 128k bytes of program memory organized in 1024 pages of 128 bytes. this memory is both parallel and serial in-system programmable (isp). isp allows devices to alter their own program memory in the actual end product under software control. a default serial loader (bootloader) program allows isp of the flash. the programming does not require external high programming voltage. the necessary high pro- gramming voltage is generated on-chip using the standard v cc pins of the microcontroller. features ? flash internal program memory. ? boot vector allows user provided flash loader code to reside anywhere in the flash memory space. this configuration provides flexibility to the user. ? default loader in boot flash allows programming via the serial port without the need of a user provided loader. ? up to 64k byte external program memory if the internal program memory is disabled (ea = 0). ? programming and erase voltage with standard 5v or 3v v cc supply. flash memory organization at89c51re2 features several on-chip memories: ?flash memory fm0: containing 128 kbytes of program memory (user space) organized into 128 bytes pages. ? boot rom rm0: 4k bytes for boot loader. ? 8k bytes internal xram
28 7663e?8051?10/08 at89c51re2 physical memory organisation figure 9. physical memory organisation on-chip flash memory the at89c51re2 implements up to 128k bytes of on-chip program/code memory. figure 9 and figure 10 shows the partitioning of internal and external program/code memory spaces accord- ing to ea value. the memory partitioning of the 8051 core microcontroller is typical a harvard architecture where program and data areas are held in separate memory areas. the program and data memory areas use the same physical address range from 0000h-ffffh and a 8 bit instruction code/data format. to access more than 64kbytes of code memory, without modifications of the mcu core, and development tools, the bank switching method is used. the internal program memory is expanded to 128kbyte in the expanded configuration?, the data memory remains in the normal configuration. the program memory is split into four 32 kbyte banks (named bank 0-2). the mcu core still addresses up to 64kbytes where the upper 32kbytes can be selected between 3 32k bytes bank of on-chip flash memory. the lower 32k bank is used as common area for interrupt subroutines, bank switching and functions calls between banks. the at89c51re2 also implements an extra upper 32k bank (bank3) that allows external code execution. 128k bytes flash memory fm0 hardware security (1 byte) column latches (128 bytes) user space extra row fm0 (128 bytes) 4k bytes rom 1ffffh 00000h rm0 fuse configuration byte(1 byte) fcb hsb
29 7663e?8051?10/08 at89c51re2 figure 10. program/code memory organization ea=1 0000h 7fffh 8000h ffffh 8000h ffffh 8000h ffffh 8000h ffffh 32k common upper 32k bank 0 upper 32k bank 1 upper 32k bank 2 upper 32k bank 3 optional external memory on-chip flash code memory external code memory 00000h 07fffh 08000h 0ffffh 10000h 17fffh 18000h 1ffffh logical mcu address physical flash address logical mcu address logical mcu address physical flash address physical flash address logical mcu address
30 7663e?8051?10/08 at89c51re2 when ea=0, the on-chip flash memory is disabled and the mcu core can address only up to 64kbyte of external memory (none of the on-chip flash memory fm0 banks or rm0 can be mapped and executed). figure 11. program/code memory organization ea=0 0000h ffffh 64k common on-chip flash code memory external code memory 00000h 0ffffh logical mcu address external physical memory address
31 7663e?8051?10/08 at89c51re2 on-chip rom bootloader the on-chip rom bootloader (rm0) is enable only for isp operations after reset (bootloader execution). the rm0 memory area belongs to a logical addressable memory space called ?bank boot?. rm0 cannot be activated from the on-chip flash memory . it means that it is not possible acti- vate the bank boot area by software (it prevents any rm0 execution and flash corruption from the user application). rm0 logical area consists in an independent code execution memory area of 4k bytes starting at logical 0x0000 address (it allows the use of the interrupts in the bootloader execution). 0000h 7fffh 8000h ffffh 8000h ffffh 8000h ffffh 8000h ffffh bank 0 on-chip flash code memory external code memory 00000h 07fffh 08000h 0ffffh 10000h 17fffh 18000h 1ffffh logical mcu address physical address logical mcu address logical mcu address physical address physical address logical mcu address bank 1 bank 2 bank 3 logical mcu address rom address bank boot (ext) 0000h on-chip rom memory (rm0) 1000h 0000h 1000h
32 7663e?8051?10/08 at89c51re2 boot process the brv2-0 bits of the fcb (see table 20 on page 34), the ea pin value upon reset and the presence of the external hardware conditions, al low to modify the default reset vector of the at89c51re2. the hardware conditions (ea = 1, psen = 0) during the reset falling edge force the on-chip bootloader execution. this allows an application to be built that will normally execute the end user?s code but can be manually forced into default isp operation. the hardware conditions allows to force the enter in isp mode whatever the configurations bits. figure 12. boot reset vector configuration ea pin hardware conditions brv2-0 mcu reset vector 0 x x external code at address 0x0000 1 yes x rm0 at address 0x0000 (atmel bootloader) no 1 1 1 fm0 at address 0x0000 with bank0 mapped 1 1 0 fm0 at address 0xfffc in bank 0 1 0 1 fm0 at address 0xfffc in bank 1 1 0 0 fm0 at address 0xfffc in bank 2 0 1 1 rm0 at address 0x0000 (atmel bootloader) 0 1 0 reserved (fm0 at address 0x0000 with bank 0 mapped) 0 0 1 0 0 0
33 7663e?8051?10/08 at89c51re2 fm0 memory architecture the fm0 flash memory is made up of 5 blocks: 1. the memory array (user space) 128k bytes 2. the extra row also called fm0 xaf 3. the hardware security bits (hsb) 4. the fuse configuration byte (fcb) 5. the column latch user space this space is composed of a 128k bytes flash memory organized in 1024 pages of 128 bytes. it contains the user?s application code. this block can be access in read/write mode from fm0 and boot memory area. (when access in write mode from fm0, the cpu core enter pseudo idle mode). extra row (xrow or xaf) this row is a part of fm0 and has a size of 128 bytes. the extra row (xaf) may contain informa- tion for boot loader usage.this block can be access in read/write mode from fm0 and boot memory area. (when access in write mode from fm0, the cpu core enter pseudo idle mode). hardware security byte (hsb) the hardware security byte is a part of fm0 and has a size of 1 byte. the 8 bits can be read/written by software (from fm0 or rm0) and written by hardware in paral- lel mode. the hsb bits can be written to ?0? without any restriction (increase the security level of the chip), but can be written to ?1? only when the corresponding memory area of the lock bits was full chip erased. table 19. hardware security byte (hsb) 76543210 - - - - - flb2 flb1 flb0 bit number bit mnemonic description 7- unused 6-4 - reserved 3- unused 2-0 flb2-0 fm0 memory lock bits see table 32 on page 52
34 7663e?8051?10/08 at89c51re2 fuse configuration byte (fcb) the fuse configuration byte is a part of fm0. the 8 bits read/written by software (from fm0 or rm0) and written by hardware in parallel mode. table 20. fuse configuration byte (fcb) 76543210 x2 - - - - brv2 brv1 brv0 bit number bit mnemonic description 7x2 x2 mode programmed (?0? value) to force x2 mode (6 clocks per instruction) after reset unprogrammed (?1? value) to force x1 mode, standard mode, after reset (default) 6-3 - unused 2-0 brv2-0- boot reset vector these bits allow to configure the reset vector of the product according to the following values: 1 1 1: reset at address 0x0000 of fm0 with bank0 mapped 1 1 0: reset at address 0xfffc of bank 0 1 0 1: reset at address 0xfffc of bank 1 1 0 0: reset at address 0xfffc of bank 2 0 1 1: reset at address 0x0000 of rm0 (internal rom bootloader execution) 0 1 0: reserved for further extension but same as 1 1 1 0 0 1: reserved for further extension but same as 1 1 1 0 0 0: reserved for further extension but same as 1 1 1
35 7663e?8051?10/08 at89c51re2 column latches the column latches, also part of fm0, has a size of one page (128 bytes). the column latches are the entrance buffers of the three previous memory locations (user array, xrow, hardware security byte and fuse configuration byte). this block is write only from fm0, rm0. cross memory access description overview the fm0 memory can be programmed from rm0 without entering idle mode. programming fm0 from fm0 makes the cpu core entering ?pseudo idle? mode. in the pseudo idle mode, the code execution is halted, the peripherals are still running (like stan- dard idle mode) but all interrupt are delayed to the end of this mode. there are fours ways of exiting pseudo idle mode: ? at the end of the regular flash programming operation ? reset the chip by external reset ? reset the chip by hardware watchdog ? reset the chip by pca watchdog programming fm0 from external memory code (ea=0 or ea=1,with bank3 active) is impossible. if a reset occurs during flash programming the target page could be incompletely erased or pro- grammed, but any other memory location (fm0, ram, xram) remain unchanged. the table 21 shows all software flash access allowed. table 21. cross memory access code executing from action fm0 (user flash) rm0 (boot rom) fm0 (user flash) read ok denied load column latch ok n.a. write ok (pseudo idle mode) n.a. rm0 (boot rom) read ok ok load column latch ok n.a. write ok n.a. external memory ea = 0 or ea=1, bank3 read (1) 1. depends of general lock bits configuration n.a. not applicable denied load column latch denied n.a. write denied n.a.
36 7663e?8051?10/08 at89c51re2 access and operations descriptions fm0 flash registers the cpu interfaces to the flash memory through the fcon register, auxr1 register and fsta register. these registers are used to map the columns latch, hsb, fcb and extra row in the working data or code space. bmsel register table 22. bmsel register bmsel register (s:92h) bank memory select reset value= 0000 0yyyb (where yyy depends on brv2:0 value in fuse configuration byte) 76543210 mbo2 mbo1 mbo0 fbs2 fbs1 fbs0 bit number bit mnemonic description 7-5 mbo2:0 memory bank operation these bits select the target memory bank fo r flash write or read operation. these bits allows to read or write the on-chip flas h memory from one upper 32k bytes to another one. 0 x x: the on-chip flash operation target banked is the same as fbs2:0 1 0 0: the target memory bank is forced to bank0 1 0 1: the target memory bank is forced to bank1 1 1 0: the target memory bank is forced to bank2 1 1 1: the target memory bank is fo rced to bank3 (optional external bank) 4-3 reserved 2-0 fbs2:0 fetch bank selection these bits select the upper 32k bytes execution bank: fbs1:0 can be read/write by software. fbs2 is read-only by software (the boot bank can not be mapped from fm0) 0 0 0 bank0 0 0 1 bank1 0 1 0 bank2 0 1 1 bank3 (optionnal external bank) 1 x x boot bank (read only) upon reset fbs2:0 is initialized according to brv2:0 configuration bits in fcb.
37 7663e?8051?10/08 at89c51re2 fcon register table 23. fcon register fcon register (s:d1h) flash control register reset value= 0000 0000b 76543210 fpl3 fpl2 fpl1 fpl0 fps fmod2 fmod1 fmod0 bit number bit mnemonic description 7-4 fpl3:0 programming launch command bits write 5xh followed by axh to launch the programming according to fmod2:0. (see table 26.) 3fps flash map program space when this bit is set: the movx @dptr, a instruction writes in the columns latches space when this bit is cleared: the movx @dptr, a instruction writes in the regular xdata memory space 2-0 fmod2:0 flash mode these bits allow to select the target memory area and operation on fm0 see table 25.
38 7663e?8051?10/08 at89c51re2 fsta register table 24. fsta register fsta register (s:d3h) flash status register reset value= ?r?xxx x000b where ?r? depends on the reset conditions: if rm0 is executed after reset r=1, if fm0 is exe- cuted after reset r=0 76543210 fmr - - - - fse fload fbusy bit number bit mnemonic description 7fmr flash movc redirection when code is executed from rm0 (and only rm0), this bit allow the movc instruction to be redirected to fm0. clear this bit to allow movc instruction to read fm0 set this bit to allow movc instruction to read rm0 this bit can be written only from rm 0 (on-chip rom bootloader execution). 6-3 - unused 2fse flash sequence error set by hardware when the flash activation sequencers fcon 5x and mov fcon ax) is not correct (see error report section) clear by software or clear by hardware if the last activation sequence was correct (previous error is canceled) 1fload flash columns latch loaded set by hardware when the first data is loaded in the column latches. clear by hardware when the activation sequence succeeds (flash write success, or reset column latch success) 0 fbusy flash busy set by hardware when progr amming is in progress. clear by hardware w hen programming is done. can not be changed by software.
39 7663e?8051?10/08 at89c51re2 mapping of the memory space by default, the user space is accessed by movc a, @a+dptr instruction for read only. setting fps bit in fcon register takes precedence on the extram bit in auxr register. the other memory spaces (user, extra row, hardware security) are made accessible in the code segment by programming bits fmod2:0 in fcon register in accordance with table 25. a movc instruction is then used for reading these spaces. thanks to the columns latches access, it is po ssible to write fm0 array, hsb and extra row blocks. the column latches space is made accessib le by setting the fps bit in fcon register. writing is possible from 0000h to ffffh, address bits 6 to 0 are used to select an address within a page while bits 14 to 7 are used to select the programming address of the page. table 25. .fm0 blocks select bits fmod2 fmod1 fmod0 adressable space 0 0 0 fm0 array(0000h-ffffh) 0 0 1 extra row(00h-80h) 0 1 0 erase fm0 0 1 1 column latches reset 100hsb 101fcb 110 reserved 111
40 7663e?8051?10/08 at89c51re2 launching flash commands (activation sequence) fpl3:0 bits in fcon register are used to secure the launch of programming. a specific sequence must be written in these bits to unlock the write protection and to launch the operation. this sequence is 5xh followed by axh. table 26 summarizes the memory spaces to program according to fmod2:0 bits. table 26. fm0 programming sequences note: 1. the sequence 5xh and axh must be executed without instructions between them otherwise the programming is not executed (see flash status register). 2. the sequence 5xh and axh can be executed with the different fmod0, fmod1 values, the last fmod1:0 value latches the destination target. 3. when the fmod2 bit is set (corresponding to the serial number field code) no write operation can be performed. 4. only the bits corresponding to the previously ?full erase? memory space can be written to one. write to fcon operation fpl3:0 fps fmod2 fmod1 fmod0 fm0 5 x 0 0 0 no action a x 0 0 0 write the column latches in fm0 xaf fm0 5 x 0 0 1 no action ax00 1 write the column latches in fm0 extra row space erase fm0 5 x 0 1 0 no action a x 0 1 0 full erase fm0 memory area reset fm0 column latches 5 x 0 1 1 no action a x 0 1 1 reset the fm0 column latches hsb 5 x 1 0 0 no action ax10 0 write the hardware security byte (hsb) see (4) fcb 5 x 1 0 1 no action ax10 1 write the fuse configuration byte (fcb) reserved 5x110 no action ax11 0 reserved 5x111 ax11 1
41 7663e?8051?10/08 at89c51re2 loading the column latches any number of data from 0 byte to 128 bytes can be loaded in the column latches. the data writ- ten in the column latches can be written in a none consecutive order. the dptr allows to select the address of the byte to load in the column latches. the page address to be written (target page in fm0) is given by the last address loaded in the column latches and when this page belongs to the upper 32k bytes of the logical addressable mcu space, the target memory bank selection is performed upon the mbo2:0 value during the last address loaded. when 0 byte is loaded in the column latches the activation sequence (5xh, axh in fcon) does not launch any operations. the fse bit in fsta register is set. when a current flash write operation is on-going (fbusy is set), it is impossible to load the col- umns latches before the end of flash programming process (the write operation in the columns latches is not performed, and the previous columns latches content is not overwritten). when programming is launched, an automatic erase of the entire memory page is first per- formed, then programming is effectively done. thus no page or block erase is needed and only the loaded data are programmed in the corresponding page. the unloaded data of the target memory page are programmed at 0xff value (automatic page erase value). the following procedure is used to load the column latches and is summarized in figure 13: ? disable interrupt and map the column latch space by setting fps bit. ? select the target memory bank (for page address larger than 32k) ? map the column latch ? reset the column latch ? load the dptr with the address to write. ? load accumulator register with the data to write. ? execute the movx @dptr, a instruction, and only this one (no movx @ri, a). ? if needed loop the last three instructions until the page is completely loaded. ? unmap the column latch if needed (it can be left mapped) and enable interrupt
42 7663e?8051?10/08 at89c51re2 figure 13. column latches loading procedure note: the last page address used when loading the column latch is the one used to select the page pro- gramming address. note: the value of mb02:0 during the last load gives the upper 32k bytes bank target selection. note: the execution of this sequence when busy flag is set leads to the no-execution of the write in the column latches (the previous loaded data remains unchanged). writing the flash spaces user the following procedure is used to program the user space and is summarized in figure 14: ? load up to one page of data in the colu mn latches from address 0000h to ffffh (see figure 13.). ? disable the interrupts. ? launch the programming by writing the data sequence 50h followed by a0h in fcon register. the end of the programming indicated by the fbusy flag cleared. ? enable the interrupts. column latches loading data load dptr= address acc= data exec: movx @dptr, a last byte to load? data memory mapping fcon = 00h (fps = 0) save & disable it ea= 0 restore it and default target memory bank select target bank mb2:0=yy column latches reset fcon= 53h (fps=0) fcon= abh (fps=1)
43 7663e?8051?10/08 at89c51re2 extra row the following procedure is used to progr am the extra row space and is summarized in figure 14: ? load data in the column latches from address ff80h to ffffh. ? disable the interrupts. ? launch the programming by writing the data sequence 51h followed by a1h in fcon register. the end of the programming indicated by the fbusy flag cleared. ? enable the interrupts. figure 14. flash and extra row programming procedure hardware security byte (hsb) the following procedure is used to program the hardware security byte space and is summarized in figure 15: ? set fps and map hardware byte (fcon = 0x0c) ? save and disable the interrupts. ? load dptr at address 0000h ? load accumulator register with the data to load. ? execute the movx @dptr, a instruction. flash programming save & disable it ea= 0 launch programming fcon= 50h fcon= a0h end programming restore it column latches loading see figure 13 fbusy cleared? clear mode fcon = 00h xrow programming save & disable it ea= 0 launch programming fcon= 51h fcon= a1h end programming restore it column latches loading see figure 13 fbusy cleared? clear mode fcon = 00h
44 7663e?8051?10/08 at89c51re2 ? launch the programming by writing the data sequence 54h followed by a4h in fcon register. the end of the programming indicated by the fbusy flag cleared. ? restore the interrupts . figure 15. hardware security byte programming procedure fuse configuration byte (fcb) the following procedure is used to program the fuse configuration byte space and is summarized in figure 16: ? set fps and map fcb (fcon = 0x0d) ? save and disable the interrupts. ? load dptr at address 0000h ? load accumulator register with the data to load. ? execute the movx @dptr, a instruction. hsb programming launch programming fcon= 54h fcon= a4h end programming restoreit fbusy cleared? clear mode fcon = 00h data load dptr= 00h acc= data exec: movx @dptr, a fcon = 0ch save & disable it ea= 0
45 7663e?8051?10/08 at89c51re2 ? launch the programming by writing the data sequence 55h followed by a5h in fcon register. the end of the programming indicated by the fbusy flag cleared. ? restore the interrupts . figure 16. fuse configuration byte programming procedure reset of columns latches space no automatic reset of the columns latches is performed after a successful flash write process. resetting the columns latches during a flash write process is mandatory. user shall implement a reset of the column latch before each column latch load sequence. fcb programming launch programming fcon= 55h fcon= a5h end programming restoreit fbusy cleared? clear mode fcon = 00h data load dptr= 00h acc= data exec: movx @dptr, a fcon = 0dh save & disable it ea= 0
46 7663e?8051?10/08 at89c51re2 in addition, the user application can reset the columns latches space manually. the fol- lowing procedure is used to reset the columns latches space launch the programming by writing the data sequence 53h followed by a3h in fcon register (from fm0 and rm0).
47 7663e?8051?10/08 at89c51re2 errors report / miscellaneous states flash busy flag the fbusy flag indicates on-going flash write operation. the busy flag is set by hardware, the hardware clears this flag after the end of the programming operation. flash programming sequence error when a wrong sequence is detected the fse in fsta is set. the following events are considered as not correct activation sequence: - the two ?mov fcon,5x and mov fcon, ax? were not consecutive, or the second instruction differs from ?mov fcon ax? (for example, an interrupt occurs during the sequence). - the sequence (write flash or reset column latches) occurred with no data loaded in the column latches the fse bit can be cleared: - by software - by hardware when a correct programming sequence occurs. note: when a good sequence occurs just after an incorrect sequence, the previous error is lost. the user software application should take care to check the fse bit before initiating a new sequence. power down mode request in power down mode, the on-chip flash memory is deselected (to reduce power consumption), this leads to the lost of the columns latches content. in this case, if columns latches were previously loaded they are reset: fload bit in fsta regis- ter should be reset after power down mode. if a power down mode is requested during flash programming (fbusy=1), all power down sequence instructions should be ignored until the end of flash process.
48 7663e?8051?10/08 at89c51re2 reading the flash spaces user the following procedure is used to read the user space: ? read one byte in accumulator by executing movc a,@a+dptr note: fcon is supposed to be reset when not needed. depending of the mbo2:0 bits, the movc a,@a+dptr can address a specific upper 32k bytes bank. it allows to read the 32k bytes upper on-chip flash memory from one bank to another one. when read from the bootloader area, the user memory shall be mapped before any read access by setting the fmr bit of the fsta register. by default, when the bootloader is entered by hardware conditions, the rom area is mapped for movc a,@a+dptr operations. it is necessary to remap the user memory before each read access. extra row (xaf) the following procedure is used to read the extra row space and is summarized in figure 17: ? map the extra row space by writing 01h in fcon register. ? read one byte in accumulator by executing movc a,@a+dptr with a= 0 & dptr= 0000h to 007fh. ? clear fcon to unmap the extra row. figure 17. xaf reading procedure hardware security byte the following procedure is used to read the hardware security space and is summa- rized in figure 18: ? map the hardware security space by writing 04h in fcon register. ? read the byte in accumulator by executing movc a,@a+dptr with a= 0 & dptr= 0000h. ? clear fcon to unmap the hardware security byte. xraw reading data read dptr= @ (00h up to 7fh acc= 0 exec: movc a, @a+dptr xraw mapping fcon = 01h xraw unmapping fcon = 00h (fps = 0)
49 7663e?8051?10/08 at89c51re2 figure 18. hsb reading procedure fuse configurationbyte the following procedure is used to read the fuse configuration byte and is summarized in figure 18: ? map the fcb by writing 05h in fcon register. ? read the byte in accumulator by executing movc a,@a+dptr with a= 0 & dptr= 0000h. ? clear fcon to unmap the hardware security byte. hsb reading procedure hsb reading data read dptr= 0000h acc= 00h exec: movc a, @a+dptr hsb mapping fcon = 04h hsb unmapping fcon = 00h (fps = 0) fcb reading data read dptr= 0000h acc= 00h exec: movc a, @a+dptr fcb mapping fcon = 05h hsb unmapping fcon = 00h (fps = 0)
50 7663e?8051?10/08 at89c51re2 operation cross memory access space addressable in read and write are: ?ram ? eram (expanded ram access by movx) ? xram (external ram) ? fm0 (user flash) ? hardware byte ?xrow fm0 ?boot rm0 ? flash column latch the table below provide the different kind of memory which can be accessed from different code location. table 27. cross memory access sharing instructions table 28. instructions shared note: by cl: using column latch action ram xram eram boot rm0 fm0 hsb fcb xaf fm0 boot rm0 read ok ok ok ok ok ok ok write ok ok - ok (rww) ok (rww) ok (rww) ok (rww) fm0 read ok ok - ok ok ok ok write ok ok - ok (idle) ok ok ok external memory ea = 0 or bank3 read ok ok - - - - - write ok ok - - - - - action ram xram rm0 cl fm0 fm0 hsb xaf fm0 read mov movx a,@dptr movc a, @a+dptr - movc a, @a+dptr movc a, @a+dptr movc a, @a+dptr write mov movx @dptr,a - movx @dptr,a by cl fm0 by cl fm0 by cl fm0
51 7663e?8051?10/08 at89c51re2 table 29. write movx @dptr,a table 30. movc a, @a+dptr executed from external code ea=0 table 31. movc a, @a+dptr executed from external code ea=1, pc>=0x8000, fbs=bank3 fps of fccon ea xram eram cl fm0 0 x winner 1 1winner 0winner fmod2:0 fbs (fetch) mbo (target) movc a,@a+dptr x x x read external code fmod2:0 mbo (target) dptr movc a,@a+dptr x x < 0x8000 depends on flb2:0 can returns random value, for secured part. x >= 0x8000 external code read
52 7663e?8051?10/08 at89c51re2 flash protection from parallel programming the three lock bits in hardware security byte (see "in-system programming" section) are pro- grammed according to table 32 provide different level of protection for the on-chip flash memory fm0. they are set by default to level 4 table 32. program lock bit flb2-0 program lock bits u: unprogrammed p: programmed warning: security level 2 and 3 should only be programmed after verification. program lock bits protection description security level flb0 flb1 flb2 1 u u u no program lock features enabled. 2puu movc instruction executed from exter nal program memory are disabled from fetching code bytes from internal memory, ea is sampled and latched on reset, and further parallel programming of the flash is disabled. isp allows only flash verification (no writ e operations are allowed) but iap from internal code still allowed. 3upu same as 2, also verify through parallel programming interface is disabled and isp read operation not allowed. 4 u u p same as 3, also external execution is disabled (external bank not accessible)
53 7663e?8051?10/08 at89c51re2 bootloader architecture introduction the bootloader manages a communication between a host platform running an isp tool and a at89c51re2 target. the bootloader implemented in at89c51re2 is designed to reside in the dedicated rom bank. this memory area can only be executed (fetched) when the processor enters the boot process. the implementation of the bootloader is based on standard set of libraries including intel hex based protocol, standard communication links and atmel isp command set. figure 19. bootloader functional description on the above diagram, the on-chip bootloader processes are: ? isp communication management the purpose of this process is to manage the communication and its protocol between the on- chip bootloader and a external device. the on-chip rom implement a serial protocol (see sec- tion bootloader protocol). this process translate serial communication frame (uart) into flash memory access (read, write, erase...). ? memory management this process manages low level access to flash memory (performs read and write access). isp communication management specific protocol communication management memory external host with memory bootloader
54 7663e?8051?10/08 at89c51re2 bootloader description entry points after reset only one bootloader entry point is possible. this entry point stands at address 0x0000 of the boot rom memory. this entry point executes the boot process of the bootloader. the bootloader entry point can be selected through two processes: at reset, if the hardware conditions are applied, the bootloader entry point is accessed and executed. at reset, if the hardware conditions are not set and the brv2-0 is programmed ?011?, the boot- loader entry point is accessed and the bootprocess is started. boot process description the boot process consists in three main operations: ? the hardware boot process request detection ? the communication link detection (uart or ocd) ? the start-up of the bootloader hardware boot process request detection the hardware boot process request is detect ed when the hardware conditions (under reset, ea=1 and psen=0) are received by the processor or when no hardware condition is applied and the brv2:0 is configured ?011?. communication link detection two interfaces are available for isp: ?uart0 ? ocd uart hardware boot process reset brv=?011? pc = rm0 @0x0000h communication link start bootloader start application brv=?100? ea=1 psen=0 yes no yes no detector / initialiser yes no brv=?101? yes no brv=?110? ye s no pc = fm0 bank2 @0xfffch pc = fm0 bank1 @0xfffch pc = fm0 bank0 @0xfffch pc = fm0 bank0 @0xfffch
55 7663e?8051?10/08 at89c51re2 the communication link detection is done by a circular polling on all the interfaces. on at89c51re2, the isp interfaces are all based on simple uart mechanisms (rx, tx). the rx line default state is ?1? when no communication is in progress. a transition from ?1? to ?0? on the rx line indicates a start of frame. once one of the interface detects a starts of frame (?0?) on its rx line, the interface is selected and configuration of the communication link starts. figure 20. communication link detection notes: 1. sf: start of frame (?0? = detected; ?1? = not detected) 2. in at89c51re2 implementation, interface 1 refers to uart0 and interface 2 refers to the ocd uart interface. yes no interface 1 sf = 0 yes no interface 2 sf = 0 detection start interface 1 initialisation interface 2 initialisation start bootloader
56 7663e?8051?10/08 at89c51re2 isp protocol description physical layer the uart used to transmit information has the following configuration: ? character: 8-bit data ? parity: none ? stop: 1 bit ? flow control: none ? baud rate: autobaud is performed by the bootloader to compute the baud rate chosen by the host. frame description the serial protocol is based on the intel extended hex-type records. intel hex records consist of ascii characters used to represent hexadecimal values and are summarized below. table 33. intel hex type frame ? record mark: ? record mark is the start of frame. this field must contain?:?. ? record length: ? record length specifies the number of bytes of information or data which follows the record type field of the record. ? load offset: ? load offset specifies the 16-bit starting load offset of the data bytes, therefore this field is used only for ? data program record. ? record type: ? record type specifies the command type. this field is used to interpret the remaining information within the frame. ? data/info: ? data/info is a variable length field. it consists of zero or more bytes encoded as pairs of hexadecimal digits. the meaning of data depends on the record type. ? checksum: ? checksum is the two?s complement of the 8-bit bytes that result from converting each pair of ascii hexadecimal digits to one byte of binary, thus including all field from the record length field to the last byte of the data/info field. therefore, the sum of all the ascii pairs in a record after converting to binary, including all field from the record length field to the checksum field, is zero. record mark ?:? record length load offset record type data or info checksum 1 byte 1 byte 2 bytes 1 bytes n byte 1 byte
57 7663e?8051?10/08 at89c51re2 protocol overview an initialization step must be performed after each reset. after microcontroller reset, the boot- loader waits for an autobaud sequence (see section ?autobaud performances?). when the communication is initialized the protocol depends on the record type issued by the host. communication initialization the host initiates the communication by sending a ?u? character to help the bootloader to com- pute the baudrate (autobaud). figure 21. initialization autobaud performances the bootloader supports a wide range of baud rates. it is also adaptable to a wide range of oscil- lator frequencies. this is accomplished by measuring the bit-time of a single bit in a received character. this information is then used to program the baud rate in terms of timer counts based on the oscillator frequency. command data stream protocol all commands are sent using the same flow. to increase performance, the echo has been removed from the bootloader response. figure 22. command flow each command flow may end with: host bootloader ?u? performs autobaud init communication if (not received ?u?) ?u? communication opened else sends back ?u? character bootloader ":" sends first character of the frame if (not received ":") sends frame (made of 2 ascii gets frame, and sends back echo for each received byte host else ":" sends echo and start reception characters per byte) echo analysis
58 7663e?8051?10/08 at89c51re2 ? ?x?: if checksum error ? ?l?: if read security is set ? ?p?: if program security is set ? ?.?: if command ok ? byte + ?.?: read byte ok
59 7663e?8051?10/08 at89c51re2 reading/blank checking memory to start the reading or blank checking operation, requests from host answers from bootloader the boot loader can answer to a read command with: ? ?address = data ?& ?cr? &?lf? the number of data by line depends of the bootloader. ? ?x? & ?cr? & ?lf? if the checksum is wrong ? ?l? & ?cr? & ?lf? if the security is set the bootloader answers to blank check command: ? ?.? & ?cr? &?lf? when the blank check is ok ? ?first address wrong? ?cr? & ?lf? when the blank check is fail ? ?x? & ?cr? & ?lf? if the checksum is wrong ? ?l? & ?cr? & ?lf? if the security is set changing memory/page to change the memory selected and/or the page, the host can send two commands. ? select new page to keep the same memory. ? select memory to change the memory and page requests from host answers from bootloader the boot loader can answer to a read command with: ? ?. ?& ?cr? &?lf? if the command is done ? ?x? & ?cr? & ?lf? if the checksum is wrong command record type record length offset data[0] data[1] data[2] data[3] data[4] read selected memory 04h 05h 0000h start address end address 00h blank check selected memory 01h command record type record length offset data[0] data[1] select new page 02h 02h start address page (4 bits) + 0h 00h select memory 04h 02h 0000h memory space page
60 7663e?8051?10/08 at89c51re2 programming/erasing memory requests from host answers from bootloader the boot loader answers with: ? ?.? & ?cr? &?lf? when the data are programmed ? ?x? & ?cr? & ?lf? if the checksum is wrong ? ?p? & ?cr? & ?lf? if the security is set starting application the application can only be started by a watchdog reset. no answer is returned by the bootloader. requests from host command record type record length offset data[0] data[1] data[2] data[3] data[4] program selected memory 00h nb of data start address xxxxx erase selected memory 04h 05h 0000h 00h ffh 00h 00h 02h command record type record length offset start application with watchdog 01h 00h 0000h
61 7663e?8051?10/08 at89c51re2 isp commands description select memory space the ? select memory space ? command allows to route all read, write commands to a selected area. for each area (family) a code is defined. this code corresponds to the memory area encoded value in the intel hex frame. the area supported and there coding are listed in the table below. table 34. memory families & coding the bootloader information and the signature areas are read only. the value in the coding col- umn is the value to report in the corresponding protocol field. note: * the coding number doesn?t include any information on the authorized address range of the fam- ily. a summary of these addresses is available in appendix (see ?address mapping? on page 67.) memory/information family coding* name flash 0 mem_flash security 7 mem_protect configuration 8 mem_conf bootloader 3 mem_boot signature 6 mem_signature
62 7663e?8051?10/08 at89c51re2 select page the ? select page ? command allows to define a page number in the selected area. a page is defined as a 64k linear memory space (according to the intel hex format). it doesn?t corre- sponds to a physical bank from the processor. the following table summarizes the memory spaces for which the select page command can be applied. table 35. memory space & select page memory/information family comments/restriction flash page 0 (0->64k) and 1(64k->128k) available
63 7663e?8051?10/08 at89c51re2 write commands the following table summarizes the memory spaces for which the write command can be applied. table 36. memory space & select page in case of write command to other area, nothing is done. the bootloader returns a write protection (?p?) if the security do not allow any write operation from the bootloader. flash the program/data flash memory area can be programmed by the bootloader by data pages of up to 128bytes. if the flash memory security level is at least ?2? (flb2:0 = ?110?), no write operation can be per- formed through the bootloader. table 37. flash write authorization summary configuration the fcb configuration byte can always be written, whatever are the security levels. security the security byte can always be written with a value that enables a protection higher than the previous one. if attempting to write a lower security, no action is performed and the bootloader returns a pro- tection error code (?p?) table 38. security write authorization summary memory/information family comments/restriction flash need security level check security only a higher level can be write configuration command security level (hsb) flb2:0 111 110 101 011 write allowed forbidden forbidden forbidden write from flb2:0 security level (hsb) to flb2:0 111 110 101 011 111 allowed allowed allowed allowed 110 forbidden allowed allowed allowed 101 forbidden forbidden allowed allowed 011 forbidden forbidden forbidden allowed
64 7663e?8051?10/08 at89c51re2 erasing commands the erasing command is supported by the following areas: table 39. memory space & erase nothing is done on the other areas. flash the erasing command on the flash memory: ? erases the four physical flash memory banks (from address 0000h to 1ffffh). ? the hsb (hardware security byte) is set at no_protection: ? flb2.0 = ?111? memory/information family comments/restriction flash need security level check
65 7663e?8051?10/08 at89c51re2 blank checking commands the blank checking command is supported by the following areas table 40. memory space & erase nothing is done on the other areas. the first not erased address is returned if the blank check is failed. flash the blank checking command on the flash memory can be done from address 0000h to 1ffffh. the blank check operation is only possible if t he hsb (hardware security byte) has a security level lower than or equal to ?2? (flb2.0 = ?110?) table 41. flash blank check authorization summary memory/information family comments/restriction flash need security level check command security level (hsb) flb2:0 111 110 101 011 blank check allowed allowed forbidden forbidden
66 7663e?8051?10/08 at89c51re2 reading commands the reading command is supported by the following areas: table 42. memory space & select page flash the reading command on the flash memory can be done from address 000h to 1ffffh. the read operation is only possible if the hsb (hardware security byte) has a security level lower than or equal to ?2? (flb2.0 = ?110?) table 43. flash read authorization summary configuration the configuration family can always be read. security the security family can always be read. bootloader all the field from the bootloared family can be read from the bootloader. each bootloader information shall be read unitary. accesses must be done byte per byte according to the address definition signature all the field from the signature family can be read from the bootloader. each signature infor- mation shall be read unitary. accesses must be done byte per byte according to the address definition memory/information family comments/restriction flash need security level check security configuration bootloader signature command security level (hsb) flb2:0 111 110 101 011 read allowed allowed forbidden forbidden
67 7663e?8051?10/08 at89c51re2 start application the start application command is used to quit the bootloader and start the application loaded. the start application is performed by a watchdog reset. the best way to start the application from a user defined entry point is to configure the fcb (fuse configuration byte) before launching the watchdog. then, depending on the configuration of the brv2:0 field, the hardware boots from the selected memory area. isp command summary uart protocol frames address mapping table 45. memory families, addresses & coding attempting an access with any other ?coding?, ?page number? or ?address? results in no action and no answer from the bootloader. table 44. summary of frames from host command record type record length offset data[0] data[1] data[2] data[3] data[4] program selected memory 00h nb of data start address xxxxx start application with watchdog 01h 00h 0000h x xxxx select new page 02h 02h start address page (4 bits) + 0h 00hxxx select memory 04h 02h 0000h memory space page x x x read selected memory 05h 0000h start address end address 00h blank check selected memory 01h erase selected memory 00h ffh 00h 00h 02h memory/parameter coding address page number memory/information family flash 0 0 up to 0x1ffff 0 up to 1 flash hsb 7 0 0 security fcb 8 0 0 configuration bootloader revision 3 00h 0 bootloader boot id1 01h boot id2 02h manuf. code 6 30h 0 signature family code 31h product name 60h product rev 61h
68 7663e?8051?10/08 at89c51re2 timers/counters the at89c51re2 implements two general-purpose, 16-bit timers/counters. such are identified as timer 0 and timer 1, and can be independently configured to operate in a variety of modes as a timer or an event counter. when operating as a timer, the timer/counter runs for a pro- grammed length of time, then issues an interrupt request. when operating as a counter, the timer/counter counts negative transitions on an ex ternal pin. after a preset number of counts, the counter issues an interrupt request. the various operating modes of each timer/counter are described in the following sections. timer/counter operations a basic operation is timer registers thx and tlx (x = 0, 1) connected in cascade to form a 16- bit timer. setting the run control bit (trx) in tcon register (see figure 46) turns the timer on by allowing the selected input to increment tl x. when tlx overflows it increments thx; when thx overflows it sets the timer overflow flag (tfx) in tcon register. setting the trx does not clear the thx and tlx timer registers. timer registers can be accessed to obtain the current count or to enter preset values. they can be read at any time but trx bit must be cleared to pre- set their values, otherwise the behavior of the timer/counter is unpredictable. the c/tx# control bit selects timer operation or counter operation by selecting the divided- down peripheral clock or external pin tx as the source for the counted signal. trx bit must be cleared when changing the mode of operation, otherwise the behavior of the timer/counter is unpredictable. for timer operation (c/tx# = 0), the timer register counts the divided-down peripheral clock. the timer register is incremented once every peripheral cycle (6 peripheral clock periods). the timer clock rate is f per /6, i.e. f osc /12 in standard mode or f osc /6 in x2 mode. for counter operation (c/tx# = 1), the timer register counts the negative transitions on the tx external input pin. the external input is sa mpled every peripheral cycles. when the sample is high in one cycle and low in the next one, the counter is incremented. since it takes 2 cycles (12 peripheral clock periods) to recognize a negative transition, the maximum count rate is f per /12, i.e. f osc /24 in standard mode or f osc /12 in x2 mode. there are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full peripheral cycle. timer 0 timer 0 functions as either a timer or event counter in four modes of operation. figure 23 to figure 26 show the logical configuration of each mode. timer 0 is controlled by the four lower bits of tmod register (see figure 47) and bits 0, 1, 4 and 5 of tcon register (see figure 46). tmod register selects the method of timer gating (gate0), timer or counter operation (t/c0#) and mode of operation (m10 and m00). tcon register pro- vides timer 0 control functions: overflow flag (tf0), run control bit (tr0), interrupt flag (ie0) and interrupt type control bit (it0). for normal timer operation (gate0 = 0), setting tr0 allows tl0 to be incremented by the selected input. setting gate0 and tr0 allows external pin int0# to control timer operation. timer 0 overflow (count rolls over from all 1s to all 0s) sets tf0 flag generating an interrupt request. it is important to stop timer/counter before changing mode.
69 7663e?8051?10/08 at89c51re2 mode 0 (13-bit timer) mode 0 configures timer 0 as an 13-bit timer wh ich is set up as an 8-bit timer (th0 register) with a modulo 32 prescaler implemented with the lower five bits of tl0 register (see figure 23). the upper three bits of tl0 register are indeterminate and should be ignored. prescaler overflow increments th0 register. figure 23. timer/counter x (x = 0 or 1) in mode 0 mode 1 (16-bit timer) mode 1 configures timer 0 as a 16-bit timer with th0 and tl0 registers connected in cascade (see figure 24). the selected input increments tl0 register. figure 24. timer/counter x (x = 0 or 1) in mode 1 ftx clock trx tcon reg tfx tcon reg 0 1 gatex tmod reg 6 overflow timer x interrupt request c/tx# tmod reg tlx (5 bits) thx (8 bits) intx# tx see the ?clock? section trx tcon reg tfx tcon reg 0 1 gatex tmod reg overflow timer x interrupt request c/tx# tmod reg tlx (8 bits) thx (8 bits) intx# tx ftx clock 6 see the ?clock? section
70 7663e?8051?10/08 at89c51re2 mode 2 (8-bit timer with auto-reload) mode 2 configures timer 0 as an 8-bit timer (tl0 register) that automatically reloads from th0 register (see figure 25). tl0 overflow sets tf0 flag in tcon register and reloads tl0 with the contents of th0, which is preset by software. when the interrupt request is serviced, hardware clears tf0. the reload leaves th0 unchanged. the next reload value may be changed at any time by writing it to th0 register. figure 25. timer/counter x (x = 0 or 1) in mode 2 mode 3 (two 8-bit timers) mode 3 configures timer 0 such that regist ers tl0 and th0 operate as separate 8-bit timers (see figure 26). this mode is provided for applications requiring an additional 8-bit timer or counter. tl0 uses the timer 0 control bits c/t0# and gate0 in tmod register, and tr0 and tf0 in tcon register in the normal manner. th0 is locked into a timer function (counting f per /6) and takes over use of the timer 1 interrupt (tf1) and run control (tr1) bits. thus, operation of timer 1 is restricted when timer 0 is in mode 3. figure 26. timer/counter 0 in mode 3: two 8-bit counters trx tcon reg tfx tcon reg 0 1 gatex tmod reg overflow timer x interrupt request c/tx# tmod reg tlx (8 bits) thx (8 bits) intx# tx ftx clock 6 see the ?clock? section tr0 tcon.4 tf0 tcon.5 int0# 0 1 gate0 tmod.3 overflow timer 0 interrupt request c/t0# tmod.2 tl0 (8 bits) tr1 tcon.6 th0 (8 bits) tf1 tcon.7 overflow timer 1 interrupt request t0 ftx clock 6 ftx clock 6 see the ?clock? section
71 7663e?8051?10/08 at89c51re2 timer 1 timer 1 is identical to timer 0 excepted for mo de 3 which is a hold-count mode. the following comments help to understand the differences: ? timer 1 functions as either a timer or event counter in three modes of operation. figure 23 to figure 25 show the logical configuration for modes 0, 1, and 2. timer 1?s mode 3 is a hold-count mode. ? timer 1 is controlled by the four high-order bits of tmod register (see figure 47) and bits 2, 3, 6 and 7 of tcon register (see figure 46). tmod register selects the method of timer gating (gate1), timer or counter operation (c/t1#) and mode of operation (m11 and m01). tcon register provides timer 1 control functions: overflow flag (tf1), run control bit (tr1), interrupt flag (ie1) and interrupt type control bit (it1). ? timer 1 can serve as the baud rate generator for the serial port. mode 2 is best suited for this purpose. ? for normal timer operation (gate1 = 0), setting tr1 allows tl1 to be incremented by the selected input. setting gate1 and tr1 allows external pin int1# to control timer operation. ? timer 1 overflow (count rolls over from all 1s to all 0s) sets the tf1 flag generating an interrupt request. ? when timer 0 is in mode 3, it uses timer 1?s overflow flag (tf1) and run control bit (tr1). for this situation, use timer 1 only for applications that do not require an interrupt (such as a baud rate generator for the serial port) and switch timer 1 in and out of mode 3 to turn it off and on. ? it is important to stop timer/counter before changing mode. mode 0 (13-bit timer) mode 0 configures timer 1 as a 13-bit timer, wh ich is set up as an 8-bit timer (th1 register) with a modulo-32 prescaler implemented with the lower 5 bits of the tl1 register (see figure 23). the upper 3 bits of tl1 register are ignored. prescaler overflow increments th1 register. mode 1 (16-bit timer) mode 1 configures timer 1 as a 16-bit timer with th1 and tl1 registers connected in cascade (see figure 24). the selected input increments tl1 register. mode 2 (8-bit timer with auto-reload) mode 2 configures timer 1 as an 8-bit timer (tl1 register) with automatic reload from th1 reg- ister on overflow (see figure 25). tl1 overflow sets tf1 flag in tcon register and reloads tl1 with the contents of th1, which is preset by software. the reload leaves th1 unchanged. mode 3 (halt) placing timer 1 in mode 3 causes it to halt and hold its count. this can be used to halt timer 1 when tr1 run control bit is not available i.e. when timer 0 is in mode 3. interrupt each timer handles one interrupt source that is the timer overflow flag tf0 or tf1. this flag is set every time an overflow occurs. flags are cleared when vectoring to the timer interrupt rou- tine. interrupts are enabled by setting etx bit in ien0 register. this assumes interrupts are globally enabled by setting ea bit in ien0 register.
72 7663e?8051?10/08 at89c51re2 figure 27. timer interrupt system tf0 tcon.5 et0 ien0.1 timer 0 interrupt request tf1 tcon.7 et1 ien0.3 timer 1 interrupt request
73 7663e?8051?10/08 at89c51re2 registers table 46. tcon register tcon (s:88h) timer/counter control register reset value = 0000 0000b 76543210 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 bit number bit mnemonic description 7 tf1 timer 1 overflow flag cleared by hardware when processor vectors to interrupt routine. set by hardware on timer/counter overflow, when timer 1 register overflows. 6tr1 timer 1 run control bit clear to turn off timer/counter 1. set to turn on timer/counter 1. 5 tf0 timer 0 overflow flag cleared by hardware when processor vectors to interrupt routine. set by hardware on timer/counter overflow, when timer 0 register overflows. 4tr0 timer 0 run control bit clear to turn off timer/counter 0. set to turn on timer/counter 0. 3ie1 interrupt 1 edge flag cleared by hardware when interrupt is processed if edge-triggered (see it1). set by hardware when external in terrupt is detected on int1# pin. 2it1 interrupt 1 type control bit clear to select low level active (level triggered) for external interrupt 1 (int1#). set to select falling edge active (edge triggered) for external interrupt 1. 1ie0 interrupt 0 edge flag cleared by hardware when interrupt is processed if edge-triggered (see it0). set by hardware when external in terrupt is detected on int0# pin. 0it0 interrupt 0 type control bit clear to select low level active (level triggered) for external interrupt 0 (int0#). set to select falling edge active (edge triggered) for external interrupt 0.
74 7663e?8051?10/08 at89c51re2 table 47. tmod register tmod (s:89h) timer/counter mode control register notes: 1. reloaded from th1 at overflow. 2. reloaded from th0 at overflow. reset value = 0000 0000b 76543210 gate1 c/t1# m11 m01 gate0 c/t0# m10 m00 bit number bit mnemonic description 7gate1 timer 1 gating control bit clear to enable timer 1 whenever tr1 bit is set. set to enable timer 1 only while int1# pin is high and tr1 bit is set. 6c/t1# timer 1 counter/timer select bit clear for timer operation: timer 1 counts the divided-down system clock. set for counter operation: timer 1 counts negative transitions on external pin t1. 5m11 timer 1 mode select bits m11 m01 operating mode 0 0 mode 0: 8-bit timer/counter (th1) with 5-bit prescaler (tl1). 0 1 mode 1: 16-bit timer/counter. 1 0 mode 2: 8-bit auto-reload timer/counter (tl1) (1) 1 1 mode 3: timer 1 halted. retains count 4m01 3gate0 timer 0 gating control bit clear to enable timer 0 whenever tr0 bit is set. set to enable timer/counter 0 only while int0# pin is high and tr0 bit is set. 2c/t0# timer 0 counter/timer select bit clear for timer operation: timer 0 counts the divided-down system clock. set for counter operation: timer 0 counts negative transitions on external pin t0. 1m10 timer 0 mode select bit m10 m00 operating mode 0 0 mode 0: 8-bit timer/counter (th0) with 5-bit prescaler (tl0). 0 1 mode 1: 16-bit timer/counter. 1 0 mode 2: 8-bit auto-reload timer/counter (tl0) (2) 1 1 mode 3: tl0 is an 8-bit timer/counter th0 is an 8-bit timer using timer 1?s tr0 and tf0 bits. 0 m00
75 7663e?8051?10/08 at89c51re2 table 48. th0 register th0 (s:8ch) timer 0 high byte register reset value = 0000 0000b table 49. tl0 register tl0 (s:8ah) timer 0 low byte register reset value = 0000 0000b table 50. th1 register th1 (s:8dh) timer 1 high byte register reset value = 0000 0000b 76543210 ???????? bit number bit mnemonic description 7:0 high byte of timer 0. 76543210 ???????? bit number bit mnemonic description 7:0 low byte of timer 0. 76543210 ???????? bit number bit mnemonic description 7:0 high byte of timer 1.
76 7663e?8051?10/08 at89c51re2 table 51. tl1 register tl1 (s:8bh) timer 1 low byte register reset value = 0000 0000b 76543210 ???????? bit number bit mnemonic description 7:0 low byte of timer 1.
77 7663e?8051?10/08 at89c51re2 timer 2 the timer 2 in the at89c51re2 is the standard c52 timer 2. it is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, th2 and tl2 are cascaded. it is controlled by t2con (table 52) and t2mod (table 53) registers. timer 2 operation is similar to timer 0 and timer 1.c/t2 selects f osc /12 (timer operation) or external pin t2 (counter operation) as the timer clock inpu t. setting tr2 allows tl2 to increment by the selected input. timer 2 has 3 operating modes: capture, au toreload and baud rate generator. these modes are selected by the combination of rclk, tclk and cp/rl2 (t2con). refer to the atmel 8-bit microcontroller hardware description for the description of capture and baud rate generator modes. timer 2 includes the following enhancements: ? auto-reload mode with up or down counter ? programmable clock-output auto-reload mode the auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic reload. if dcen bit in t2mod is cleared, timer 2 behaves as in 80c52 (refer to the atmel c51 microcontroller hardware description). if dcen bit is set, timer 2 acts as an up/down timer/counter as shown in figure 28. in this mode the t2ex pin controls the direction of count. when t2ex is high, timer 2 counts up. timer overflow occurs at ffffh which sets the tf2 flag and generates an interrupt request. the overflow also causes the 16-bit value in rcap2h and rcap2l registers to be loaded into the timer registers th2 and tl2. when t2ex is low, timer 2 counts down. timer underflow occurs when the count in the timer registers th2 and tl2 equals the value stored in rcap2h and rcap2l registers. the under- flow sets tf2 flag and reloads ffffh into the timer registers. the exf2 bit toggles when timer 2 overflows or underflows according to the direction of the count. exf2 does not generate any interrupt. this bit can be used to provide 17-bit resolution.
78 7663e?8051?10/08 at89c51re2 figure 28. auto-reload mode up/down counter (dcen = 1) programmable clock-output in the clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (see figure 29). the input clock increments tl2 at frequency f clk periph /2.the timer repeatedly counts to overflow from a loaded value. at overflow, the contents of rcap2h and rcap2l reg- isters are loaded into th2 and tl2.in this mode, timer 2 overflows do not generate interrupts. the formula gives the clock-out frequency as a function of the system oscillator frequency and the value in the rcap2h and rcap2l registers: for a 16 mhz system clock, timer 2 has a programmable frequency range of 61 hz (f clk periph /2 16 ) to 4 mhz (f clk periph /4). the generated clock signal is brought out to t2 pin (p1.0). timer 2 is programmed for the clock-out mode as follows: ? set t2oe bit in t2mod register. ?clear c/t2 bit in t2con register. ? determine the 16-bit reload value from the formula and enter it in rcap2h/rcap2l registers. ? enter a 16-bit initial value in timer registers th2/tl2.it can be the same as the reload value or a different one depending on the application. ? to start the timer, set tr2 run control bit in t2con register. it is possible to use timer 2 as a baud rate generator and a clock generator simultaneously. for this configuration, the baud rates and clock frequencies are not independent since both func- tions use the values in the rcap2h and rcap2l registers. (down counting reload value) c/t2 tf2 tr2 t2 exf2 th2 (8-bit) tl2 (8-bit) rcap2h (8-bit) rcap2l ( 8-bit) ffh (8-bit) ffh (8-bit) toggle (up counting reload value) timer 2 interrupt f clk periph 0 1 t2con t2con t2con t2con t2ex: if dcen=1, 1=up if dcen=1, 0=down if dcen = 0, up counting : 6 clock o ? utfrequency f clkperiph 4 65536 rcap 2 h rcap 2 l ?) ? ( -------------------------------------------------------------------------------------------- - =
79 7663e?8051?10/08 at89c51re2 figure 29. clock-out mode c/t2 = 0 :6 exf2 tr2 over- flow t2ex th 2 (8-bit) tl2 (8-bit) timer 2 rcap2h (8-bit) rcap2l (8-bit) t2oe t2 fclk periph t2con t2con t2con t2mod interrupt qd to g g l e exen2
80 7663e?8051?10/08 at89c51re2 registers table 52. t2con register t2con - timer 2 control register (c8h) reset value = 0000 0000b bit addressable 76543210 tf2 exf2 rclk tclk exen2 tr2 c/t2# cp/rl2# bit number bit mnemonic description 7tf2 timer 2 overflow flag must be cleared by software. set by hardware on timer 2 overflow, if rclk = 0 and tclk = 0. 6exf2 timer 2 external flag set when a capture or a reload is caused by a negative transition on t2ex pin if exen2=1. when set, causes the cpu to vector to timer 2 interrupt routine when timer 2 interrupt is enabled. must be cleared by software. exf2 doesn?t c ause an interrupt in up/down counter mode (dcen = 1). 5 rclk receive clock bit cleared to use timer 1 overflow as receiv e clock for serial port in mode 1 or 3. set to use timer 2 overflow as receive clock for serial port in mode 1 or 3. 4tclk transmit clock bit cleared to use timer 1 overflow as transmit clock for serial port in mode 1 or 3. set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3. 3exen2 timer 2 external enable bit cleared to ignore events on t2ex pin for timer 2 operation. set to cause a capture or reload when a negativ e transition on t2ex pin is detected, if timer 2 is not used to clock the serial port. 2tr2 timer 2 run control bit cleared to turn off timer 2. set to turn on timer 2. 1c/t2# timer/counter 2 select bit cleared for timer operation (input from internal clock system: f clk periph ). set for counter operation (input from t2 input pin, falling edge trigger). must be 0 for clock out mode. 0 cp/rl2# timer 2 capture/reload bi t if rclk=1 or tclk=1, cp/rl2# is ignored and timer is forced to auto-reload on timer 2 overflow. cleared to auto-reload on timer 2 overflows or negative transitions on t2ex pin if exen2=1. set to capture on negative transitions on t2ex pin if exen2=1.
81 7663e?8051?10/08 at89c51re2 table 53. t2mod register t2mod - timer 2 mode control register (c9h) reset value = xxxx xx00b not bit addressable 76543210 ------t2oedcen bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6- reserved the value read from this bit is indeterminate. do not set this bit. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4- reserved the value read from this bit is indeterminate. do not set this bit. 3- reserved the value read from this bit is indeterminate. do not set this bit. 2- reserved the value read from this bit is indeterminate. do not set this bit. 1t2oe timer 2 output enable bit cleared to program p1.0/t2 as clock input or i/o port. set to program p1.0/t2 as clock output. 0dcen down counter enable bit cleared to disable timer 2 as up/down counter. set to enable timer 2 as up/down counter.
82 7663e?8051?10/08 at89c51re2 programmable counter array pca the pca provides more timing capabilities with less cpu intervention than the standard timer/counters. its advantages include reduced software overhead and improved accuracy. the pca consists of a dedicated timer/counter which serves as the time base for an array of five compare/capture modules. its clock input can be programmed to count any one of the following signals: ? peripheral clock frequency (f clk periph ) 6 ? peripheral clock frequency (f clk periph ) 2 ? timer 0 overflow ? external input on eci (p1.2) each compare/capture modules can be programmed in any one of the following modes: ? rising and/or falling edge capture ? software timer ? high-speed output ? pulse width modulator module 4 can also be programmed as a watchdog timer (see section "pca watchdog timer", page 93). when the compare/capture modules are programmed in the capture mode, software timer, or high speed output mode, an interrupt can be generated when the module executes its function. all five modules plus the pca timer overflow share one interrupt vector. the pca timer/counter and compare/capture modules share port 1 for external i/o. these pins are listed below. if the port is not used for the pca, it can still be used for standard i/o. the pca timer is a common time base for all five modules (see figure 30). the timer count source is determined from the cps1 and cps0 bits in the cmod register (table 54) and can be programmed to run at: ? 1/6 the peripheral clock frequency (f clk periph ) ? 1/2 the peripheral clock frequency (f clk periph ) ? the timer 0 overflow ? the input on the eci pin (p1.2) pca component external i/o pin 16-bit counter p1.2 / eci 16-bit module 0 p1.3 / cex0 16-bit module 1 p1.4 / cex1 16-bit module 2 p1.5 / cex2 16-bit module 3 p1.6 / cex3
83 7663e?8051?10/08 at89c51re2 figure 30. pca timer/counter cidl cps1 cps0 ecf it ch cl 16 bit up/down counter to pca modules fclk periph /6 fclk periph / 2 t0 ovf p1.2 idle cmod 0xd9 wdte cf cr ccon 0xd8 ccf4 ccf3 ccf2 ccf1 ccf0 overflow
84 7663e?8051?10/08 at89c51re2 table 54. cmod register cmod - pca counter mode register (d9h) reset value = 00xx x000b not bit addressable the cmod register includes three additional bits associated with the pca (see figure 30 and table 54). ? the cidl bit which allows the pca to stop during idle mode. ? the wdte bit which enables or disables the watchdog function on module 4. ? the ecf bit which when set causes an interrupt and the pca overflow flag cf (in the ccon sfr) to be set when the pca timer overflows. the ccon register contains the run control bit for the pca and the flags for the pca timer (cf) and each module (refer to table 55). ? bit cr (ccon.6) must be set by software to run the pca. the pca is shut off by clearing this bit. ? bit cf: the cf bit (ccon.7) is set when the pca counter overflows and an interrupt will be generated if the ecf bit in the cmod register is set. the cf bit can only be cleared by software. ? bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. these flags also can only be cleared by software. 76543210 cidl wdte - - - cps1 cps0 ecf bit number bit mnemonic description 7cidl counter idle control cleared to program the pca counter to continue functioning during idle mode. set to program pca to be gated off during idle. 6wdte watchdog timer enable cleared to disable watchdog timer function on pca module 4. set to enable watchdog timer function on pca module 4. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4- reserved the value read from this bit is indeterminate. do not set this bit. 3- reserved the value read from this bit is indeterminate. do not set this bit. 2cps1 pca count pulse select cps1 cps0 selected pca input 0 0 internal clock fclk periph/6 0 1 internal clock fclk periph/2 1 0 timer 0 overflow 1 1 external clock at eci/p1.2 pin (max rate = fclk periph/ 4) 1cps0 0ecf pca enable counter overflow interrupt cleared to disable cf bit in ccon to inhibit an interrupt. set to enable cf bit in ccon to generate an interrupt.
85 7663e?8051?10/08 at89c51re2 table 55. ccon register ccon - pca counter control register (d8h) reset value = 00x0 0000b not bit addressable the watchdog timer function is implemented in module 4 (see figure 33). the pca interrupt system is shown in figure 31. 76543210 cf cr - ccf4 ccf3 ccf2 ccf1 ccf0 bit number bit mnemonic description 7cf pca counter overflow flag set by hardware when the counter rolls over. cf flags an interrupt if bit ecf in cmod is set. cf may be set by either hardware or softw are but can only be cleared by software. 6cr pca counter run control bit must be cleared by software to turn the pca counter off. set by software to turn the pca counter on. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4 ccf4 pca module 4 interrupt flag must be cleared by software. set by hardware when a ma tch or capture occurs. 3 ccf3 pca module 3 interrupt flag must be cleared by software. set by hardware when a ma tch or capture occurs. 2 ccf2 pca module 2 interrupt flag must be cleared by software. set by hardware when a ma tch or capture occurs. 1 ccf1 pca module 1 interrupt flag must be cleared by software. set by hardware when a ma tch or capture occurs. 0 ccf0 pca module 0 interrupt flag must be cleared by software. set by hardware when a ma tch or capture occurs.
86 7663e?8051?10/08 at89c51re2 figure 31. pca interrupt system pca modules: each one of the five compare/capture modules has six possible functions. it can perform: ? 16-bit capture, positive-edge triggered ? 16-bit capture, negative-edge triggered ? 16-bit capture, both positive and negative-edge triggered ? 16-bit software timer ? 16-bit high speed output ? 8-bit pulse width modulator in addition, module 4 can be used as a watchdog timer. each module in the pca has a special function register associated with it. these registers are: ccapm0 for module 0, ccapm1 for module 1, etc. (see table 56). the registers contain the bits that control the mode that each module will operate in. ? the eccf bit (ccapmn.0 where n=0, 1, 2, 3, or 4 depending on the module) enables the ccf flag in the ccon sfr to generate an interrupt when a match or compare occurs in the associated module. ? pwm (ccapmn.1) enables the pulse width modulation mode. ? the tog bit (ccapmn.2) when set causes the cex output associated with the module to toggle when there is a match between the pca counter and the module's capture/compare register. ? the match bit mat (ccapmn.3) when set will cause the ccfn bit in the ccon register to be set when there is a match between the pca counter and the module's capture/compare register. ? the next two bits capn (ccapmn.4) and capp (ccapmn.5) determine the edge that a capture input will be active on. the capn bit enables the negative edge, and the capp bit enables the positive edge. if both bits are set both edges will be enabled and a capture will occur for either transition. ? the last bit in the register ecom (ccapmn.6) when set enables the comparator function. table 56 shows the ccapmn settings for the various pca functions. cf cr ccon 0xd8 ccf4 ccf3 ccf2 ccf1 ccf0 module 4 module 3 module 2 module 1 module 0 ecf pca timer/counter eccfn ccapmn.0 cmod.0 ie.6 ie.7 to interrupt priority decoder ec ea
87 7663e?8051?10/08 at89c51re2 table 56. ccapmn registers (n = 0-4) ccapm0 - pca module 0 compare/capture control register (0dah) ccapm1 - pca module 1 compare/capture control register (0dbh) ccapm2 - pca module 2 compare/capture control register (0dch) ccapm3 - pca module 3 compare/capture control register (0ddh) ccapm4 - pca module 4 compare/capture control register (0deh) reset value = x000 0000b not bit addressable 76543210 - ecomn cappn capnn matn togn pwmn eccfn bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6ecomn enable comparator cleared to disable the comparator function. set to enable the comparator function. 5 cappn capture positive cleared to disable positive edge capture. set to enable positive edge capture. 4capnn capture negative cleared to disable negative edge capture. set to enable negative edge capture. 3matn match when matn = 1, a match of the pca count er with this module's compare/capture register causes the ccfn bit in ccon to be set, flagging an interrupt. 2 togn toggle when togn = 1, a match of the pca counter with this module's compare/capture register causes the cexn pin to toggle. 1pwmn pulse width modulation mode cleared to disable the cexn pin to be used as a pulse width modulated output. set to enable the cexn pin to be used as a pulse width modulated output. 0 ccf0 enable ccf interrupt cleared to disable compare/capture flag ccfn in the ccon register to generate an interrupt. set to enable compare/capture flag ccfn in the ccon register to generate an interrupt.
88 7663e?8051?10/08 at89c51re2 table 57. pca module modes (ccapmn registers) there are two additional registers associated with each of the pca modules. they are ccapnh and ccapnl and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. when a module is used in the pwm mode these registers are used to control the duty cycle of the output (see table 58 & table 59). table 58. ccapnh registers (n = 0-4) ccap0h - pca module 0 compare/capture control register high (0fah) ccap1h - pca module 1 compare/capture control register high (0fbh) ccap2h - pca module 2 compare/capture control register high (0fch) ccap3h - pca module 3 compare/capture control register high (0fdh) ccap4h - pca module 4 compare/capture control register high (0feh) reset value = 0000 0000b not bit addressable ecomn cappn capnn matn togn pwmm eccfn module function 0000000 no operation x10000x 16-bit capture by a positive-edge trigger on cexn x01000x 16-bit capture by a negative trigger on cexn x 1 1 0 0 0 x 16-bit capture by a transition on cexn 100100x 16-bit software timer / compare mode. 1 0 0 1 1 0 x 16-bit high speed output 1000010 8-bit pwm 1 0 0 1 x 0 x watchdog timer (module 4 only) 76543210 -------- bit number bit mnemonic description 7-0 - pca module n compare/capture control ccapnh value
89 7663e?8051?10/08 at89c51re2 table 59. ccapnl registers (n = 0-4) ccap0l - pca module 0 compare/capture control register low (0eah) ccap1l - pca module 1 compare/capture control register low (0ebh) ccap2l - pca module 2 compare/capture control register low (0ech) ccap3l - pca module 3 compare/capture control register low (0edh) ccap4l - pca module 4 compare/capture control register low (0eeh) reset value = 0000 0000b not bit addressable table 60. ch register ch - pca counter register high (0f9h) reset value = 0000 0000b not bit addressable table 61. cl register cl - pca counter register low (0e9h) reset value = 0000 0000b not bit addressable 76543210 -------- bit number bit mnemonic description 7-0 - pca module n compare/capture control ccapnl value 76543210 -------- bit number bit mnemonic description 7-0 - pca counter ch value 76543210 -------- bit number bit mnemonic description 7-0 - pca counter cl value
90 7663e?8051?10/08 at89c51re2 pca capture mode to use one of the pca modules in the capture mode either one or both of the ccapm bits capn and capp for that module must be set. the external cex input for the module (on port 1) is sampled for a transition. when a valid transition occurs the pca hardware loads the value of the pca counter registers (ch and cl) into the module's capture registers (ccapnl and ccapnh). if the ccfn bit for the module in the ccon sfr and the eccfn bit in the ccapmn sfr are set then an interrupt will be generated (refer to figure 32). figure 32. pca capture mode 16-bit software timer/ compare mode the pca modules can be used as software time rs by setting both the ecom and mat bits in the modules ccapmn register. the pca timer will be compared to the module's capture regis- ters and when a match occurs an interrupt will occur if the ccfn (ccon sfr) and the eccfn (ccapmn sfr) bits for the module are both set (see figure 33). cf cr ccon 0xd8 ch c l cc ap nh c ca pn l ccf4 ccf3 ccf2 ccf1 ccf0 pca it pca coun te r/timer ecomn ccapmn, n= 0 to 4 0xda to 0xde capnn matn togn pwmn eccfn cappn cex.n capture
91 7663e?8051?10/08 at89c51re2 figure 33. pca compare mode and pca watchdog timer before enabling ecom bit, ccapnl and ccapnh should be set with a non zero value, other- wise an unwanted match could happen. writing to ccapnh will set the ecom bit. once ecom set, writing ccapnl will clear ecom so that an unwanted match doesn?t occur while modifying the compare value. writing to ccapnh will set ecom. for this reason, user software should write ccapnl first, and then ccapnh. of course, the ecom bit can still be controlled by accessing to ccapmn register. high speed output mode in this mode the cex output (on port 1) associated with the pca module will toggle each time a match occurs between the pca counter and the module's capture registers. to activate this mode the tog, mat, and ecom bits in the module's ccapmn sfr must be set (see figure 34). a prior write must be done to ccapnl and ccapnh before writing the ecomn bit. ch c l cc ap nh c ca pn l ecomn cc a pm n, n = 0 to 4 0xda to 0xde ca pnn ma tn togn pwmn e ccfn ca ppn 16 bit comparator ma tch cc on 0xd8 pca i t en ab le pca cou nte r/ time r reset * cidl cps1 cps0 ecf cm od 0xd9 wdte reset write to ccapnl wr ite t o ccapnh cf ccf2 ccf1 ccf0 cr ccf3 ccf4 10
92 7663e?8051?10/08 at89c51re2 figure 34. pca high speed output mode before enabling ecom bit, ccapnl and ccapnh should be set with a non zero value, other- wise an unwanted match could happen. once ecom set, writing ccapnl will clear ecom so that an unwanted match doesn?t occur while modifying the compare value. writing to ccapnh will set ecom. for this reason, user software should write ccapnl first, and then ccapnh. of course, the ecom bit can still be controlled by accessing to ccapmn register. pulse width modulator mode all of the pca modules can be used as pwm outputs. figure 35 shows the pwm function. the frequency of the output depends on the source for the pca timer. all of the modules will have the same frequency of output because they all share the pca timer. the duty cycle of each module is independently variable using the module's capture register ccapln. when the value of the pca cl sfr is less than the value in the module's ccapln sfr the output will be low, when it is equal to or greater than the output will be high. when cl overflows from ff to 00, ccapln is reloaded with the value in ccaphn. this allows updating the pwm without glitches. the pwm and ecom bits in the module's ccapmn register must be set to enable the pwm mode. ch cl cca pnh ccapnl ecomn cca pmn, n = 0 to 4 0xda to 0xde capnn matn togn p wmn eccfn cappn 1 6 b it comp ar ato r ma tch cf cr ccon 0xd8 ccf4 ccf3 ccf2 ccf1 ccf0 pca it enable cexn p ca counte r/time r write to ccapnh reset write to ccapnl 1 0
93 7663e?8051?10/08 at89c51re2 figure 35. pca pwm mode pca watchdog timer an on-board watchdog timer is available with the pca to improve the reliability of the system without increasing chip count. watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge. module 4 is the only pca module that can be programmed as a watchdog. however, this module can still be used for other modes if the watchdog is not needed. figure 33 shows a diagram of how the watchdog works. the user pre- loads a 16-bit value in the compare registers. just like the other compare modes, this 16-bit value is compared to the pca timer value. if a match is allowed to occur, an internal reset will be generated. this will not cause the rst pin to be driven high. in order to hold off the reset, the user has three options: 1. periodically change the compare value so it will never match the pca timer, 2. periodically change the pca timer value so it will never match the compare values, or 3. disable the watchdog by clearing the wdte bit before a match occurs and then re-enable it. the first two options are more reliable because the watchdog timer is never disabled as in option #3. if the program counter ever goes astray, a match will eventually occur and cause an internal reset. the second option is also not recommended if other pca modules are being used. remember, the pca timer is the time base for all modules; changing the time base for other modules would not be a good idea. thus, in most applications the first solution is the best option. this watchdog timer won?t generate a reset out on the reset pin. cl ccapnh ccapnl ecomn ccapmn, n= 0 to 4 0xda to 0xde capnn matn togn pwmn eccfn cappn 8 bit comparator cexn ?0? ?1? enable pca counter/timer overflow
94 7663e?8051?10/08 at89c51re2 serial i/o port the serial i/o ports in the at89c51re2 are compatible with the serial i/o port in the 80c52. they provide both synchronous and asynchronous communication modes. they operates as a universal asynchronous receiver and transmitter (uart) in three full-duplex modes (modes 1, 2 and 3). asynchronous transmission and recepti on can occur simultaneously and at different baud rates both serial i/o port include the following enhancements: ? framing error detection ? automatic address recognition as these improvements apply to both uart, most of the time in the following lines, there won?t be any reference to uart_0 or uart_1, but only to uart, generally speaking. framing error detection framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). to enable the framing bit error detection feature, set smod0 bit in pcon register (see figure 36) for uart 0 or set smod0_1 in bdrcon_1 register for uart 1 (see figure 37). figure 36. uart 0 framing error block diagram figure 37. uart 1 framing error block diagram when this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. an invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two cpus. if a valid stop bit is not found, the framing error bit (fe) in scon register (see table 68.) bit is set. software may examine fe bit after each reception to check for data errors. once set, only soft- ware or a reset can clear fe bit. subsequently received frames with valid stop bits cannot clear fe bit. when fe feature is enabled, ri rises on stop bit instead of the last data bit (see figure 38 and figure 39). to uart 0 framing error control sm0 to uart 0 mode control (smod0 = 0) set fe bit if stop bit is 0 (framing error) (smod0 = 1) scon_0 (98h) pcon (87h) sm0/fe sm1 sm2 ren tb8 rb8 ti ri sm0d1 smod0 - pof gf1 gf0 pd idl to uart 1 framing error control sm0 to uart 1 mode control (smod0_1 = 0) set fe_1 bit if stop bit is 0 (framing error) (smod0_1 = 1) scon_1 (c0h) bdrcon_1 (87h) sm0_1/fe_1 sm1_1 sm2_1 ren_1 tb8_1 rb8_1 ti_1 ri_1 sm0d1_1 smod0_1 - brr_1 tbck_1 rbck_1 spd_1 src_1
95 7663e?8051?10/08 at89c51re2 figure 38. uart timings in mode 1 figure 39. uart timings in modes 2 and 3 automatic address recognition the automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (sm2 bit in scon register is set). implemented in hardware, automatic address recognition enhances the multiprocessor commu- nication feature by allowing the serial port to examine the address of each incoming command frame. only when the serial port recognizes its own address, the receiver sets ri bit in scon register to generate an interrupt. this ensures that the cpu is not interrupted by command frames addressed to other devices. if desired, the user may enable the automatic address recognition feature in mode 1.in this con- figuration, the stop bit takes the place of the ninth data bit. bit ri is set only when the received command frame address matches the device?s address and is terminated by a valid stop bit. to support automatic address recognition, a device is identified by a given address and a broad- cast address. note: the multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i. e. setting sm2 bit in scon register in mode 0 has no effect). given address each device has an individual address that is specified in saddr register; the saden register is a mask byte that contains don?t-care bits (defined by zeros) to form the device?s given address. the don?t-care bits provide the flexibility to address one or more slaves at a time. the following example illustrates how a given address is formed. to address a device by its individual address, the saden mask byte must be 1111 1111b . for example: saddr0101 0110b saden 1111 1 100b given0101 01xxb the following is an example of how to use given addresses to address different slaves: data byte ri smod0=x stop bit start bit rxd d7 d6 d5 d4 d3 d2 d1 d0 fe smod0=1 ri smod0=0 data byte ninth bit stop bit start bit rxd d8 d7 d6 d5 d4 d3 d2 d1 d0 ri smod0=1 fe smod0=1
96 7663e?8051?10/08 at89c51re2 slave a:saddr1111 0001b saden 1111 1010b given1111 0x0xb slave b:saddr1111 0011b saden 1111 1001b given1111 0xx1b slave c:saddr1111 0010b saden 1111 1 101b given1111 00x1b the saden byte is selected so that each slave may be addressed separately. for slave a, bit 0 (the lsb) is a don?t-care bit; for slaves b and c, bit 0 is a 1.to communicate with slave a only, the master must send an address where bit 0 is clear (e.g.. 1111 0000b ). for slave a, bit 1 is a 1; for slaves b and c, bit 1 is a don?t care bit. to communicate with slaves b and c, but not slave a, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b ). to communicate with slaves a, b and c, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b ). broadcast address a broadcast address is formed from the logical or of the saddr and saden registers with zeros defined as don?t-care bits, e.g.: saddr0101 0110b saden1111 1 100b broadcast =saddr or saden1111 111xb the use of don?t-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is ffh. t he following is an exampl e of using broadcast addresses: slave a:saddr1111 0001b saden 1111 1010b broadcast 1111 1x11b, slave b:saddr1111 0011b saden 1111 1001b broadcast 1111 1x11b, slave c:saddr=1111 0011b saden 1111 1 101b broadcast 1111 1111b for slaves a and b, bit 2 is a don?t care bit; for slave c, bit 2 is set. to communicate with all of the slaves, the master must send an address ffh. to communicate with slaves a and b, but not slave c, the master can send and address fbh. reset addresses on reset, the saddr and saden registers are initialized to 00h, i. e. the given and broadcast addresses are xxxx xxxxb (all don?t-care bits). this ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80c51 microcontrollers that do not support automatic address recognition.
97 7663e?8051?10/08 at89c51re2 registers table 62. saden_0 register saden - slave address mask register uart 0(b9h) reset value = 0000 0000b not bit addressable table 63. saddr_0 register saddr - slave address register uart 0(a9h) reset value = 0000 0000b not bit addressable table 64. saden_1 register saden_1 - slave address mask register uart 1(bah) reset value = 0000 0000b not bit addressable table 65. saddr_1 register saddr_1 - slave address register uart 1(aah) reset value = 0000 0000b not bit addressable 76543210 76543210 76543210 76543210
98 7663e?8051?10/08 at89c51re2 baud rate selection for uart 0 for mode 1 and 3 the baud rate generator for transmit and receive clocks can be selected separately via the t2con and bdrcon_0 registers. figure 40. baud rate selection for uart 0 table 66. baud rate selection table uart 0 tclk (t2con) rclk (t2con) tbck (bdrcon) rbck (bdrcon) clock source uart tx clock source uart rx 0000timer 1timer 1 1000timer 2timer 1 0100timer 1timer 2 1100timer 2timer 2 x 0 1 0 int_brg timer 1 x 1 1 0 int_brg timer 2 0 x 0 1 timer 1 int_brg 1 x 0 1 timer 2 int_brg x x 1 1 int_brg int_brg rclk / 16 rbck int_brg 0 1 timer1 0 1 0 1 timer2 int_brg timer1 timer2 timer_brg_rx rx clock_0 / 16 0 1 timer_brg_tx tx clock_0 tbck tclk
99 7663e?8051?10/08 at89c51re2 baud rate selection for uart 1 for mode 1 and 3 the baud rate generator for transmit and receive clocks can be selected separately via the t2con and bdrcon_1 registers. figure 41. baud rate selection for uart 1 table 67. baud rate selection table uart 1 tclk (t2con) rclk (t2con) tbck_1 (bdrcon_1) rbck_1 (bdrcon_1) clock source uart tx_1 clock source uart rx_1 0000timer 1timer 1 1000timer 2timer 1 0100timer 1timer 2 1100timer 2timer 2 x 0 1 0 int_brg_1 timer 1 x 1 1 0 int_brg_1 timer 2 0 x 0 1 timer 1 int_brg_1 1 x 0 1 timer 2 int_brg_1 x x 1 1 int_brg_1 int_brg_1 rclk / 16 rbck_1 int_brg1 0 1 timer1 0 1 0 1 timer2 int_brg1 timer1 timer2 timer_brg_rx rx clock_1 / 16 0 1 timer_brg_tx tx clock_1 tbck_1 tclk
100 7663e?8051?10/08 at89c51re2 internal baud rate generator (brg) the at89c51re2 implements two internal baudrate generators. each one is dedicated to the corresponding uart. the configuration and operating mode for both brg are similar. when an internal baud rate generator is used, the baud rates are determined by the brg overflow depending on the brl (brl or brl_1 registers) reload value, the value of spd (or spd_1) bit (speed mode) in bdrcon (bdrcon_1) register and the value of the smod1 bit in pcon register. figure 42. internal baud rate generator 0 figure 43. internal baud rate generator 1 ? the baud rate for uart is token by formula: spd_0 brg 0 1 /6 brl_0 /2 0 1 int_brg brr_0 smod1 auto reload counter overflow f per brg 0 1 /6 brl_1 /2 0 1 int_brg1 spd_1 brr_1 smod1_1 auto reload counter overflow f per baud_rate = 6 (1-spd) ? 32 ? (256 -brl) 2 smod1 ? f per brl = 256 - 6 (1-spd) ? 32 ? baud_rate 2 smod1 ? f per
101 7663e?8051?10/08 at89c51re2 table 68. scon_0 register scon_0 - serial control register for uart 0(98h) reset value = 0000 0000b bit addressable 76543210 fe/sm0_0 sm1_0 sm2_0 ren_0 tb8_0 rb8_0 ti_0 ri_0 bit number bit mnemonic description 7 fe_0 framing error bit (smod0=1 ) clear to reset the error state, not cleared by a valid stop bit. set by hardware when an invalid stop bit is detected. smod0 must be set to enable access to the fe bit. sm0_0 serial port mode bit 0 refer to sm1_0 for serial port mode selection. smod0_0 must be cleared to enable access to the sm0_0 bit. 6 sm1_0 serial port mode bit 1 sm0 sm1 mode description baud rate 0 0 0 shift register f cpu periph /6 0 1 1 8-bit uart variable 10 29-bit uartf cpu periph /32 or /16 1 1 3 9-bit uart variable 5 sm2_0 serial port mode 2 bit / multiprocessor communication enable bit clear to disable multiprocessor communication feature. set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1.this bit should be cleared in mode 0. 4ren_0 reception enable bit clear to disable serial reception. set to enable serial reception. 3 tb8_0 transmitter bit 8 / ninth bit to transmit in modes 2 and 3 clear to transmit a logic 0 in the 9th bit. set to transmit a logic 1 in the 9th bit. 2 rb8_0 receiver bit 8 / ninth bit received in modes 2 and 3 cleared by hardware if 9th bit received is a logic 0. set by hardware if 9th bit received is a logic 1. in mode 1, if sm2_0 = 0, rb8 is the received stop bit. in mode 0 rb8 is not used. 1ti_0 transmit interrupt flag clear to acknowledge interrupt. set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. 0ri_0 receive interrupt flag clear to acknowledge interrupt. set by hardware at the end of the 8th bit time in mode 0, see figure 38. and figure 39. in the other modes.
102 7663e?8051?10/08 at89c51re2 table 69. scon_1 register scon_1 - serial control register for uart 1(c0h) reset value = 0000 0000b bit addressable 76543210 fe/sm0_1 sm1_1 sm2_1 ren_1 tb8_1 rb8_1 ti_1 ri_1 bit number bit mnemonic description 7 fe_1 framing error bit (smod0=1 ) clear to reset the error state, not cleared by a valid stop bit. set by hardware when an invalid stop bit is detected. smod0_1 must be set to enable access to the fe_1 bit. sm0_1 serial port mode bit 0 refer to sm1_1 for serial port mode selection. smod0_1 must be cleared to enable access to the sm0_1 bit. 6 sm1_1 serial port mode bit 1 sm0 sm1 mode description baud rate 0 0 0 shift register f cpu periph /6 0 1 1 8-bit uart variable 10 29-bit uartf cpu periph /32 or /16 1 1 3 9-bit uart variable 5 sm2_1 serial port mode 2 bit / multiprocessor communication enable bit clear to disable multiprocessor communication feature. set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1.this bit should be cleared in mode 0. 4ren_1 reception enable bit clear to disable serial reception. set to enable serial reception. 3 tb8_1 transmitter bit 8 / ninth bit to transmit in modes 2 and 3 clear to transmit a logic 0 in the 9th bit. set to transmit a logic 1 in the 9th bit. 2 rb8_1 receiver bit 8 / ninth bit received in modes 2 and 3 cleared by hardware if 9th bit received is a logic 0. set by hardware if 9th bit received is a logic 1. in mode 1, if sm2_1 = 0, rb8 is the received stop bit. in mode 0 rb8 is not used. 1ti_1 transmit interrupt flag clear to acknowledge interrupt. set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. 0ri_1 receive interrupt flag clear to acknowledge interrupt. set by hardware at the end of the 8th bit time in mode 0, see figure 38. and figure 39. in the other modes.
103 7663e?8051?10/08 at89c51re2 table 70. example of computed value when x2=1, smod1=1, spd=1 table 71. example of computed value when x2=0, smod1=0, spd=0 the baud rate generator can be used for mode 1 or 3 (refer to figure 40.), but also for mode 0 for uart, thanks to the bit src loca ted in bdrcon register (table 78.) uart registers table 72. sbuf_0 register sbuf_0 - serial buffer register for uart 0(99h) reset value = xxxx xxxxb table 73. brl_0 register brl_0 - baud rate reload register for the internal baud rate generator 0 (9ah) reset value = 0000 0000b baud rates f osc = 16. 384 mhz f osc = 24mhz brl error (%) brl error (%) 115200 247 1.23 243 0.16 57600 238 1.23 230 0.16 38400 229 1.23 217 0.16 28800 220 1.23 204 0.16 19200 203 0.63 178 0.16 9600 149 0.31 100 0.16 4800 43 1.23 - - baud rates f osc = 16. 384 mhz f osc = 24mhz brl error (%) brl error (%) 4800 247 1.23 243 0.16 2400 238 1.23 230 0.16 1200 220 1.23 202 3.55 600 185 0.16 152 0.16 76543210 76543210
104 7663e?8051?10/08 at89c51re2 table 74. sbuf_1 register sbuf - serial buffer register for uart 1(c1h) reset value = xxxx xxxxb table 75. brl_1 register brl - baud rate reload register for the internal baud rate generator 1 (bbh) reset value = 0000 0000b 76543210 76543210
105 7663e?8051?10/08 at89c51re2 table 76. t2con register t2con - timer 2 control register (c8h) reset value = 0000 0000b bit addressable 76543210 tf2 exf2 rclk tclk exen2 tr2 c/t2# cp/rl2# bit number bit mnemonic description 7tf2 timer 2 overflow flag must be cleared by software. set by hardware on timer 2 overflow, if rclk = 0 and tclk = 0. 6exf2 timer 2 external flag set when a capture or a reload is caused by a negative transition on t2ex pin if exen2=1. when set, causes the cpu to vector to timer 2 interrupt routine when timer 2 interrupt is enabled. must be cleared by software. exf2 doesn?t cause an interrupt in up/down counter mode (dcen = 1) 5rclk receive clock bit for uart cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3. set to use timer 2 overflow as receive clock for serial port in mode 1 or 3. 4tclk transmit clock bit for uart cleared to use timer 1 overflow as transmit clock for serial port in mode 1 or 3. set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3. 3exen2 timer 2 external enable bit cleared to ignore events on t2ex pin for timer 2 operation. set to cause a capture or reload when a negativ e transition on t2ex pin is detected, if timer 2 is not used to clock the serial port. 2tr2 timer 2 run control bit cleared to turn off timer 2. set to turn on timer 2. 1c/t2# timer/counter 2 select bit cleared for timer operation (input from internal clock system: f clk periph ). set for counter operation (input from t2 input pin, falling edge trigger). must be 0 for clock out mode. 0 cp/rl2# timer 2 capture/reload bit if rclk=1 or tclk=1, cp/rl2# is ignored and timer is forced to auto-reload on timer 2 overflow. cleared to auto-reload on timer 2 overflows or negative transitions on t2ex pin if exen2=1. set to capture on negative transitions on t2ex pin if exen2=1.
106 7663e?8051?10/08 at89c51re2 table 77. pcon register pcon - power control register (87h) reset value = 00x1 0000b not bit addressable power-off flag reset value will be 1 only after a power on (cold reset). a warm reset doesn?t affect the value of this bit. 76543210 smod1_0 smod0_0 - pof gf1 gf0 pd idl bit number bit mnemonic description 7 smod1_0 serial port mode bit 1 for uart set to select double baud rate in mode 1, 2 or 3. 6 smod0_0 serial port mode bit 0 for uart cleared to select sm0 bit in scon register. set to select fe bit in scon register. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4pof power-off flag cleared to recognize next reset type. set by hardware when vcc rises from 0 to its nominal voltage. can also be set by software. 3gf1 general purpose flag cleared by user for general purpose usage. set by user for general purpose usage. 2gf0 general purpose flag cleared by user for general purpose usage. set by user for general purpose usage. 1pd power-down mode bit cleared by hardware when reset occurs. set to enter power-down mode. 0idl idle mode bit cleared by hardware when interrupt or reset occurs. set to enter idle mode.
107 7663e?8051?10/08 at89c51re2 table 78. bdrcon_0 register bdrcon_0 - baud rate control register (9bh) reset value = xxx0 0000b not bit addressable 76543210 - - - brr_0 tbck_0 rbck_0 spd_0 src_0 bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit 6- reserved the value read from this bit is indeterminate. do not set this bit 5- reserved the value read from this bit is indeterminate. do not set this bit. 4 brr_0 baud rate run control bit cleared to stop the internal baud rate generator. set to start the internal baud rate generator. 3 tbck_0 transmission baud rate generator selection bit for uart cleared to select timer 1 or timer 2 for the baud rate generator. set to select internal baud rate generator. 2rbck_0 reception baud rate generator selection bit for uart cleared to select timer 1 or timer 2 for the baud rate generator. set to select internal baud rate generator. 1 spd_0 baud rate speed control bit for uart cleared to select the slow baud rate generator. set to select the fast baud rate generator. 0 src_0 baud rate source select bit in mode 0 for uart cleared to select f osc /12 as the baud rate generator (f clk periph /6 in x2 mode). set to select the internal baud rate generator for uarts in mode 0.
108 7663e?8051?10/08 at89c51re2 table 79. bdrcon_1 register bdrcon - baud rate control register (bch) reset value = 0000 0000b not bit addressable 76543210 smod1_1 smod0_1 - brr_1 tbck_1 rbck_1 spd_1 src_1 bit number bit mnemonic description 7 smod1_1 serial port mode bit 1 for uart 1 set to select double baud rate in mode 1, 2 or 3. 6 smod0_1 serial port mode bit 0 for uart 1 cleared to select sm0 bit in scon register. set to select fe bit in scon register. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4 brr_1 baud rate run control bit cleared to stop the internal baud rate generator. set to start the internal baud rate generator. 3 tbck_1 transmission baud rate generator selection bit for uart 1 cleared to select timer 1 or timer 2 for the baud rate generator. set to select internal baud rate generator. 2rbck_1 reception baud rate generator selection bit for uart 1 cleared to select timer 1 or timer 2 for the baud rate generator. set to select internal baud rate generator. 1 spd_1 baud rate speed control bit for uart 1 cleared to select the slow baud rate generator. set to select the fast baud rate generator. 0 src_1 baud rate source select bit in mode 0 for uart 1 cleared to select f osc /12 as the baud rate generator (f clk periph /6 in x2 mode). set to select the internal baud rate generator for uarts in mode 0.
109 7663e?8051?10/08 at89c51re2 interrupt system the at89c51re2 has a total of 10 interrupt vectors: two external interrupts (int0 and int1 ), three timer interrupts (timers 0, 1 and 2), two serial ports interrupts, spi interrupt, keyboard interrupt and the pca global interrupt. these interrupts are shown in figure 44. figure 44. interrupt control system each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the interrupt enable register (table 84 and table 82). this register also contains a global dis- able bit, which must be cleared to disable all interrupts at once. each interrupt source can also be individually pr ogrammed to one out of four priority levels by setting or clearing a bit in the interrupt priority register (table 85) and in the interrupt priority high register (table 83 and table 84) shows the bi t values and priority levels associated with each combination. ie1 0 3 high priority interrupt interrupt polling sequence, decreasing from high to low priority low priority interrupt global disable individual enable exf2 tf2 ti ri tf0 int0 int1 tf1 iph, ipl ie0 0 3 0 3 0 3 0 3 0 3 0 3 pca it kbd it spi it 0 3 0 3 ti_1 ri_1 0 3 twi it 0 3
110 7663e?8051?10/08 at89c51re2 registers table 80. priority level bit values a low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-prior- ity interrupt. a high-priority interrupt can?t be interrupted by any other interrupt source. if two interrupt requests of different priority levels are received simultaneously, the request of higher priority level is serviced. if interrupt requests of the same priority level are received simul- taneously, an internal polling sequence determines which request is serviced. thus within each priority level there is a second priority structure determined by the polling sequence. iph. x ipl. x interrupt level priority 0 0 0 (lowest) 011 102 1 1 3 (highest)
111 7663e?8051?10/08 at89c51re2 table 81. ien0 register ien0 - interrupt enable register (a8h) reset value = 0000 0000b bit addressable 76543210 ea ec et2 es et1 ex1 et0 ex0 bit number bit mnemonic description 7ea enable all interrupt bit cleared to disable all interrupts. set to enable all interrupts. 6ec pca interrupt enable bit cleared to disable. set to enable. 5et2 timer 2 overflow interrupt enable bit cleared to disable timer 2 overflow interrupt. set to enable timer 2 overflow interrupt. 4es serial port 0 enable bit cleared to disable serial port interrupt. set to enable serial port interrupt. 3et1 timer 1 overflow interrupt enable bit cleared to disable timer 1 overflow interrupt. set to enable timer 1 overflow interrupt. 2ex1 external interrupt 1 enable bit cleared to disable external interrupt 1. set to enable external interrupt 1. 1et0 timer 0 overflow interrupt enable bit cleared to disable timer 0 overflow interrupt. set to enable timer 0 overflow interrupt. 0ex0 external interrupt 0 enable bit cleared to disable external interrupt 0. set to enable external interrupt 0.
112 7663e?8051?10/08 at89c51re2 table 82. ipl0 register ipl0 - interrupt priority register (b8h) reset value = x000 0000b bit addressable 76543210 - ppcl pt2l psl pt1l px1l pt0l px0l bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6ppcl pca interrupt priority bit refer to ppch for priority level. 5pt2l timer 2 overflow interrupt priority bit refer to pt2h for priority level. 4psl serial port 0 priority bit refer to psh for priority level. 3pt1l timer 1 overflow interrupt priority bit refer to pt1h for priority level. 2px1l external interrupt 1 priority bit refer to px1h for priority level. 1pt0l timer 0 overflow interrupt priority bit refer to pt0h for priority level. 0px0l external interrupt 0 priority bit refer to px0h for priority level.
113 7663e?8051?10/08 at89c51re2 table 83. iph0 register iph0 - interrupt priority high register (b7h) reset value = x000 0000b not bit addressable 76543210 - ppch pt2h psh pt1h px1h pt0h px0h bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6ppch pca interrupt priority high bit. ppch ppcl priority level 0 0 lowest 01 10 1 1 highest 5pt2h timer 2 overflow interrupt priority high bit pt2h pt2l priority level 0 0 lowest 01 10 1 1 highest 4psh serial port priority high bit psh psl priority level 0 0 lowest 0 1 1 0 1 1 highest 3pt1h timer 1 overflow interrupt priority high bit pt1h pt1l priority level 0 0 lowest 01 10 1 1 highest 2px1h external interrupt 1 priority high bit px1h px1l priority level 0 0 lowest 01 10 1 1 highest 1pt0h timer 0 overflow interrupt priority high bit pt0h pt0l priority level 0 0 lowest 0 1 10 1 1 highest 0px0h external interrupt 0 priority high bit px0h px0l priority level 0 0 lowest 01 10 1 1 highest
114 7663e?8051?10/08 at89c51re2 table 84. ien1 register ien1 - interrupt enable register (b1h) reset value = xxxx 00x0b bit addressable 76543210 - - - - es_1 espi etwi ekbd bit number bit mnemonic description 7- reserved 6- reserved 5- reserved 4- reserved 3es_1 serial port 1 enable bit cleared to disable serial port interrupt. set to enable serial port interrupt. 2espi spi interrupt enable bit cleared to disable spi interrupt. set to enable spi interrupt. 1etwi twi interrupt enable bit cleared to disable twi interrupt. set to enable twi interrupt. 0ekbd keyboard interrupt enable bit cleared to disable keyboard interrupt. set to enable keyboard interrupt.
115 7663e?8051?10/08 at89c51re2 table 85. ipl1 register ipl1 - interrupt priority register (b2h) reset value = xxxx 00x0b bit addressable 76543210 - - - - psl_1 spil twil kbdl bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6- reserved the value read from this bit is indeterminate. do not set this bit. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4- reserved the value read from this bit is indeterminate. do not set this bit. 3 psl_1 serial port 1 priority bit refer to psh_1 for priority level. 2spil spi interrupt priority bit refer to spih for priority level. 1twil twi interrupt priority bit refer to twih for priority level. 0kbdl keyboard interrupt priority bit refer to kbdh for priority level.
116 7663e?8051?10/08 at89c51re2 table 86. iph1 register iph1 - interrupt priority high register (b3h) reset value = xxxx 00x0b not bit addressable 76543210 - - - - psh_1 spih twih kbdh bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6- reserved the value read from this bit is indeterminate. do not set this bit. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4- reserved the value read from this bit is indeterminate. do not set this bit. 3psh_1 serial port 1 priority high bit psh_1 psl_1 priority level 0 0 lowest 0 1 1 0 1 1 highest 2spih spi interrupt priority high bit spih spil priority level 0 0 lowest 0 1 1 0 1 1 highest 1twih twi interrupt priority high bit twih twil priority level 0 0 lowest 0 1 1 0 1 1 highest 0kbdh keyboard interrupt priority high bit kb dh kbdl priority level 0 0 lowest 0 1 10 1 1 highest
117 7663e?8051?10/08 at89c51re2 interrupt sources and vector addresses table 87. interrupt sources and vector addresses number polling priority interrupt source interrupt request vector address 0 0 reset 0000h 1 1 int0 ie0 0003h 2 2 timer 0 tf0 000bh 3 3 int1 ie1 0013h 4 4 timer 1 if1 001bh 5 6 uart0 ri+ti 0023h 6 7 timer 2 tf2+exf2 002bh 7 5 pca cf + ccfn (n = 0-4) 0033h 8 8 keyboard kbdit 003bh 9 9 twi twiit 0043h 10 10 spi spiit 004bh 11 11 uart1 ri_1+ti_1 0053h
118 7663e?8051?10/08 at89c51re2 power management introduction two power reduction modes are implemented in the at89c51re2. the idle mode and the power-down mode. these modes are detailed in the following sections. in addition to these power reduction modes, the clocks of the core and peripherals can be dynamically divided by 2 using the x2 mode detailed in section ?enhanced features?, page 13. idle mode idle mode is a power reduction mode that reduces the power consumption. in this mode, pro- gram execution halts. idle mode freezes the clock to the cpu at known states while the peripherals continue to be clocked. the cpu status before entering idle mode is preserved, i.e., the program counter and program status word register retain their data for the duration of idle mode. the contents of the sfrs and ram are also retained. the status of the port pins during idle mode is detailed in table 88. entering idle mode to enter idle mode, set the idl bit in pcon register (see table 89). the at89c51re2 enters idle mode upon execution of the instruction that sets idl bit. the instruction that sets idl bit is the last instruction executed. note: if idl bit and pd bit are set simultaneously, the at89c51re2 enters power-down mode. then it does not go in idle mode when exiting power-down mode. exiting idle mode there are two ways to exit idle mode: 1. generate an enabled interrupt. ? hardware clears idl bit in pcon register which restores the clock to the cpu. execution resumes with the interrupt service routine. upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated idle mode. the general purpose flags (gf1 and gf0 in pcon register) may be used to indicate whether an interrupt occurred during normal operation or during idle mode. when idle mode is exited by an interrupt, the interrupt service routine may examine gf1 and gf0. 2. generate a reset. ? a logic high on the rst pin clears idl bit in pcon register directly and asynchronously. this restores the clock to the cpu. program execution momentarily resumes with the instruction immediately following the instruction that activated the idle mode and may continue for a number of clock cycles before the internal reset algorithm takes control. reset initializes the at89c51re2 and vectors the cpu to address c:0000h. note: during the time that execution resumes, the internal ram cannot be accessed; however, it is pos- sible for the port pins to be accessed. to avoid unexpected outputs at the port pins, the instruction immediately following the instruction that activated idle mode should not write to a port pin or to the external ram. power-down mode the power-down mode places the at89c51re2 in a very low power state. power-down mode stops the oscillator, freezes all clock at known states. the cpu status prior to entering power- down mode is preserved, i.e., the program counter, program status word register retain their data for the duration of power-down mode. in addition, the sfr and ram contents are pre- served. the status of the port pins during power-down mode is detailed in table 88. note: vcc may be reduced to as low as v ret during power-down mode to further reduce power dissi- pation. take care, however, that vdd is not reduced until power-down mode is invoked.
119 7663e?8051?10/08 at89c51re2 entering power-down mode to enter power-down mode, set pd bit in pcon register. the at89c51re2 enters the power- down mode upon execution of the instruction that sets pd bit. the instruction that sets pd bit is the last instruction executed. exiting power-down mode note: if vcc was reduced during the power-down mode, do not exit power-down mode until vcc is restored to the normal operating level. there are two ways to exit the power-down mode: 1. generate an enabled external interrupt. ? the at89c51re2 provides capability to exit from power-down using int0#, int1#. hardware clears pd bit in pcon register which starts the oscillator and restores the clocks to the cpu and peripherals. using intx# input, execution resumes when the input is released (see figure 45). execution resumes with the interrupt service routine. upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated power-down mode. note: the external interrupt used to exit power-down mode must be configured as level sensitive (int0# and int1#) and must be assigned the highest priority. in addition, the duration of the inter- rupt must be long enough to allow the oscillator to stabilize. the execution will only resume when the interrupt is deasserted. note: exit from power-down by external interrupt does not affect the sfrs nor the internal ram content. figure 45. power-down exit waveform using int1:0# 2. generate a reset. ? a logic high on the rst pin clears pd bit in pcon register directly and asynchronously. this starts the oscillator and restores the clock to the cpu and peripherals. program execution momentarily resumes with the instruction immediately following the instruction that activated power-down mode and may continue for a number of clock cycles before the internal reset algorithm takes control. reset initializes the at89c51re2 and vectors the cpu to address 0000h. note: during the time that execution resumes, the internal ram cannot be accessed; however, it is pos- sible for the port pins to be accessed. to avoid unexpected outputs at the port pins, the instruction immediately following the instruction that activated the power-down mode should not write to a port pin or to the external ram. note: exit from power-down by reset redefines all the sfrs , but does not affect the internal ram content. int1:0# osc power-down phase oscillator restart phase active phase active phase
120 7663e?8051?10/08 at89c51re2 table 88. pin conditions in special operating modes mode port 0 port 1 port 2 port 3 port 4 ale psen# reset floating high high high high high high idle (internal code) data data data data data high high idle (external code) floating data data data data high high power-down (internal code) data data data data data low low power-down (external code) floating data data data data low low
121 7663e?8051?10/08 at89c51re2 registers table 89. pcon register pcon (87:h) power configuration register reset value= xxxx 0000b 76543210 smod1 smod0 - pof gf1 gf0 pd idl bit number bit mnemonic description 7smod1 serial port mode bit 1 set to select double baud rate in mode 1, 2 or 3. 6smod0 serial port mode bit 0 cleared to select sm0 bit in scon register. set to select fe bit in scon register. 5 - reserved 4pof power-off flag cleared to recognize next reset type. set by hardware when vcc rises from 0 to its nominal voltage. can also be set by software. 3gf1 general purpose flag 1 one use is to indicate whether an interrupt occurred during normal operation or during idle mode. 2gf0 general purpose flag 0 one use is to indicate whether an interrupt occurred during normal operation or during idle mode. 1pd power-down mode bit cleared by hardware when an interrupt or reset occurs. set to activate the power-down mode. if idl and pd are both set, pd takes precedence. 0idl idle mode bit cleared by hardware when an interrupt or reset occurs. set to activate the idle mode. if idl and pd are both set, pd takes precedence.
122 7663e?8051?10/08 at89c51re2 oscillator to optimize the power consumption and executi on time needed for a specific task, an internal prescaler feature has been implemented between the oscillator and the cpu and peripherals. registers table 90. ckrl register ckrl ? clock reload register (97h) reset value = 1111 1111b not bit addressable table 91. pcon register pcon ? power control register (87h) reset value = 00x1 0000b not bit addressable 76543210 ckrl7 ckrl6 ckrl5 ckrl4 ckrl3 ckrl2 ckrl1 ckrl0 bit number mnemonic description 7:0 ckrl clock reload register prescaler value 76543210 smod1 smod0 - pof gf1 gf0 pd idl bit number bit mnemonic description 7smod1 serial port mode bit 1 set to select double baud rate in mode 1, 2 or 3. 6smod0 serial port mode bit 0 cleared to select sm0 bit in scon register. set to select fe bit in scon register. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4pof power-off flag cleared by software to recognize the next reset type. set by hardware when v cc rises from 0 to its nominal voltage. can also be set by software. 3gf1 general-purpose flag cleared by software for general-purpose usage. set by software for general-purpose usage. 2gf0 general-purpose flag cleared by software for general-purpose usage. set by software for general-purpose usage. 1pd power-down mode bit cleared by hardware when reset occurs. set to enter power-down mode. 0idl idle mode bit cleared by hardware when interrupt or reset occurs. set to enter idle mode.
123 7663e?8051?10/08 at89c51re2 functional bloc k diagram figure 46. functional oscillator block diagram prescaler divider ? a hardware reset puts the prescaler divider in the following state: ? ckrl = ffh: f clk cpu = f clk periph = f osc /2 (standard c51 feature) ? any value between ffh down to 00h can be written by software into ckrl register in order to divide frequency of the selected oscillator: ? ckrl = 00h: minimum frequency f clk cpu = f clk periph = f osc /1020 (standard mode) f clk cpu = f clk periph = f osc /510 (x2 mode) ? ckrl = ffh: maximum frequency f clk cpu = f clk periph = f osc /2 (standard mode) f clk cpu = f clk periph = f osc (x2 mode) f clk cpu and f clk periph in x2 mode, for ckrl<>0xff: in x1 mode, for ckrl<>0xff then: xtal2 xtal1 osc clk idle cpu clock ckrl reload 8-bit prescaler-divider reset peripheral clock :2 x2 0 1 f osc ckcon0 clk periph cpu ckrl = 0xff? 0 1 f cpu f = clkperiph f osc 2 255 ckrl ? () ----------------------------------------------- = f cpu f = clkperiph f osc 4 255 ckrl ? () ----------------------------------------------- =
124 7663e?8051?10/08 at89c51re2 hardware watchdog timer the wdt is intended as a recovery method in situations where the cpu may be subjected to software upset. the wdt consists of a 14-bit counter and the watchdog timer reset (wdtrst) sfr. the wdt is by default disabled from exiting re set. to enable the wdt, user must write 01eh and 0e1h in sequence to the wdtrst, sfr location 0a6h. when wdt is enabled, it will increment every machine cycle while the oscillator is running and there is no way to disable the wdt except through reset (either hardware reset or wdt overflow reset). when wdt overflows, it will drive an output reset high pulse at the rst-pin. using the wdt to enable the wdt, user must write 01eh and 0e1h in sequence to the wdtrst, sfr loca- tion 0a6h. when wdt is enabled, the user needs to service it by writing to 01eh and 0e1h to wdtrst to avoid wdt overflow. the 14-bit c ounter overflows when it reaches 16383 (3fffh) and this will reset the device. when wdt is enabled, it will increment every machine cycle while the oscillator is running. this means the user must reset the wdt at least every 16383 machine cycle. to reset the wdt the user must write 01eh and 0e1h to wdtrst. wdtrst is a write only register. the wdt counter cannot be read or written. when wdt overflows, it will generate an output reset pulse at the rst-pin. the reset pulse duration is 96 x t clk periph , where t clk periph = 1/f clk periph . to make the best use of the wdt, it should be serviced in those sec- tions of code that will periodically be executed within the time required to prevent a wdt reset. to have a more powerful wdt, a 2 7 counter has been added to extend the time-out capability, ranking from 16ms to 2s @ f osca = 12mhz. to manage this feature, refer to wdtprg register description, table 92. table 92. wdtrst register wdtrst - watchdog reset register (0a6h) reset value = xxxx xxxxb write only, this sfr is used to reset/enable the wdt by writing 01eh then 0e1h in sequence. 76543210 --------
125 7663e?8051?10/08 at89c51re2 table 93. wdtprg register wdtprg - watchdog timer out register (0a7h) reset value = xxxx x000 wdt during power down and idle in power down mode the oscillator stops, which means the wdt also stops. while in power down mode the user does not need to service the wdt. there are 2 methods of exiting power down mode: by a hardware reset or via a level activated external interrupt which is enabled prior to entering power down mode. when power down is exited with hardware reset, servicing the wdt should occur as it normally should whenever the at89c51re2 is reset. exiting power down with an interrupt is significantly different. the interrupt is held low long enough for the oscillator to stabilize. when the interrupt is brought high, the interrupt is serviced. to prevent the wdt from resetting the device while the interrupt pin is held low, the wdt is not started until the interrupt is pulled high. it is suggested that the wdt be reset during the interrupt service routine. to ensure that the wdt does not overflow within a few states of exiting of powerdown, it is bet- ter to reset the wdt just before entering powerdown. in the idle mode, the oscillator continues to run. to prevent the wdt from resetting the at89c51re2 while in idle mode, the user should always set up a timer that will periodically exit idle, service the wdt, and re-enter idle mode. 76543210 -----s2s1s0 bit number bit mnemonic description 7- reserved the value read from this bit is undetermined. do not try to set this bit. 6- 5- 4- 3- 2s2 wdt time-out select bit 2 1s1 wdt time-out select bit 1 0s0 wdt time-out select bit 0 s2 s1 s0 selected time-out 00 0 (2 14 - 1) machine cycles, 16. 3 ms @ f osca =12 mhz 00 1 (2 15 - 1) machine cycles, 32.7 ms @ f osca =12 mhz 01 0 (2 16 - 1) machine cycles, 65. 5 ms @ f osca =12 mhz 01 1 (2 17 - 1) machine cycles, 131 ms @ f osca =12 mhz 10 0 (2 18 - 1) machine cycles, 262 ms @ f osca =12 mhz 10 1 (2 19 - 1) machine cycles, 542 ms @ f osca =12 mhz 11 0 (2 20 - 1) machine cycles, 1.05 s @ f osca =12 mhz 11 1 (2 21 - 1) machine cycles, 2.09 s @ f osca =12 mhz
126 7663e?8051?10/08 at89c51re2 reduced emi mode the ale signal is used to demultiplex address and data buses on port 0 when used with exter- nal program or data memory. nevertheless, during internal code execution, ale signal is still generated. in order to reduce emi, ale signal can be disabled by setting ao bit. the ao bit is located in auxr register at bit location 0. as soon as ao is set, ale is no longer output but remains active during movx and movc instructions and external fetches. during ale disabling, ale pin is weakly pulled high. table 94. auxr register auxr - auxiliary register (8eh) reset value = xx00 10?hsb. xram?0b not bit addressable 76543210 - - m0 xrs2 xrs1 xrs0 extram ao bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6- reserved the value read from this bit is indeterminate. do not set this bit. 5m0 pulse length cleared to stretch movx control: the rd/ and the wr/ pulse length is 6 clock periods (default). set to stretch movx control: the rd/ and the wr/ pulse length is 30 clock periods. 4xrs2 xram size xrs2 xrs1 xrs0 xram size 0 0 0 256 bytes 0 0 1 512 bytes 0 1 0 768 bytes(default) 0 1 1 1024 bytes 1 0 0 1792 bytes 3xrs1 2xrs0 1extram extram bit cleared to access internal xram using movx @ ri/ @ dptr. set to access external memory. programmed by hardware after power-up regarding hardware security byte (hsb), default setting, xram selected. 0ao ale output bit cleared, ale is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if x2 mode is used). (default) set, ale is active only during a movx or movc instruction is used.
127 7663e?8051?10/08 at89c51re2 keyboard interface the at89c51re2 implements a keyboard interface allowing the connection of a 8 x n matrix keyboard. it is based on 8 inputs with programmable interrupt capability on both high or low level. these inputs are available as alternate function of p1 and allow to exit from idle and power down modes. the keyboard interface interfaces with the c51 core through 3 special function registers: kbls, the keyboard level selection register (table 97), kbe, the keyboard interrupt enable register (table 96), and kbf, the keyboard flag register (table 95). interrupt the keyboard inputs are considered as 8 independent interrupt sources sharing the same inter- rupt vector. an interrupt enable bit (kbd in ie1) allows global enable or disable of the keyboard interrupt (see figure 47). as detailed in figure 48 each keyboard input has the capability to detect a programmable level according to kbls. x bit value. level detection is then reported in interrupt flags kbf. x that can be masked by software using kbe. x bits. this structure allow keyboard arrangement from 1 by n to 8 by n matrix and allow usage of p1 inputs for other purpose. figure 47. keyboard interface block diagram figure 48. keyboard input circuitry power reduction mode p1 inputs allow exit from idle and power down modes as detailed in section ?power manage- ment?, page 118. p1:x kbe. x kbf. x kbls. x 0 1 vcc internal pullup p1.0 keyboard interface interrupt request kbd ie1 input circuitry p1.1 input circuitry p1.2 input circuitry p1.3 input circuitry p1.4 input circuitry p1.5 input circuitry p1.6 input circuitry p1.7 input circuitry kbdit
128 7663e?8051?10/08 at89c51re2 registers table 95. kbf register kbf - keyboard flag register (9eh) reset value= 0000 0000b 76543210 kbf7 kbf6 kbf5 kbf4 kbf3 kbf2 kbf1 kbf0 bit number bit mnemonic description 7kbf7 keyboard line 7 flag set by hardware when the port line 7 detects a programmed level. it generates a keyboard interrupt request if the kbkbie. 7 bit in kbie register is set. must be cleared by software. 6kbf6 keyboard line 6 flag set by hardware when the port line 6 detects a programmed level. it generates a keyboard interrupt request if the kbie. 6 bit in kbie register is set. must be cleared by software. 5kbf5 keyboard line 5 flag set by hardware when the port line 5 detects a programmed level. it generates a keyboard interrupt request if the kbie. 5 bit in kbie register is set. must be cleared by software. 4kbf4 keyboard line 4 flag set by hardware when the port line 4 detects a programmed level. it generates a keyboard interrupt request if the kbie. 4 bit in kbie register is set. must be cleared by software. 3kbf3 keyboard line 3 flag set by hardware when the port line 3 detects a programmed level. it generates a keyboard interrupt request if the kbie. 3 bit in kbie register is set. must be cleared by software. 2kbf2 keyboard line 2 flag set by hardware when the port line 2 detects a programmed level. it generates a keyboard interrupt request if the kbie. 2 bit in kbie register is set. must be cleared by software. 1kbf1 keyboard line 1 flag set by hardware when the port line 1 detects a programmed level. it generates a keyboard interrupt request if the kbie. 1 bit in kbie register is set. must be cleared by software. 0kbf0 keyboard line 0 flag set by hardware when the port line 0 detects a programmed level. it generates a keyboard interrupt request if the kbie. 0 bit in kbie register is set. must be cleared by software.
129 7663e?8051?10/08 at89c51re2 table 96. kbe register kbe-keyboard input enable register (9dh) reset value= 0000 0000b 76543210 kbe7 kbe6 kbe5 kbe4 kbe3 kbe2 kbe1 kbe0 bit number bit mnemonic description 7kbe7 keyboard line 7 enable bit cleared to enable standard i/o pin. set to enable kbf. 7 bit in kbf register to generate an interrupt request. 6kbe6 keyboard line 6 enable bit cleared to enable standard i/o pin. set to enable kbf. 6 bit in kbf register to generate an interrupt request. 5kbe5 keyboard line 5 enable bit cleared to enable standard i/o pin. set to enable kbf. 5 bit in kbf register to generate an interrupt request. 4kbe4 keyboard line 4 enable bit cleared to enable standard i/o pin. set to enable kbf. 4 bit in kbf register to generate an interrupt request. 3kbe3 keyboard line 3 enable bit cleared to enable standard i/o pin. set to enable kbf. 3 bit in kbf register to generate an interrupt request. 2kbe2 keyboard line 2 enable bit cleared to enable standard i/o pin. set to enable kbf. 2 bit in kbf register to generate an interrupt request. 1kbe1 keyboard line 1 enable bit cleared to enable standard i/o pin. set to enable kbf. 1 bit in kbf register to generate an interrupt request. 0kbe0 keyboard line 0 enable bit cleared to enable standard i/o pin. set to enable kbf. 0 bit in kbf register to generate an interrupt request.
130 7663e?8051?10/08 at89c51re2 table 97. kbls register kbls-keyboard level selector register (9ch) reset value= 0000 0000b 76543210 kbls7 kbls6 kbls5 kbls4 kbl s3 kbls2 kbls1 kbls0 bit number bit mnemonic description 7kbls7 keyboard line 7 level selection bit cleared to enable a low level detection on port line 7. set to enable a high level detection on port line 7. 6kbls6 keyboard line 6 level selection bit cleared to enable a low level detection on port line 6. set to enable a high level detection on port line 6. 5kbls5 keyboard line 5 level selection bit cleared to enable a low level detection on port line 5. set to enable a high level detection on port line 5. 4kbls4 keyboard line 4 level selection bit cleared to enable a low level detection on port line 4. set to enable a high level detection on port line 4. 3kbls3 keyboard line 3 level selection bit cleared to enable a low level detection on port line 3. set to enable a high level detection on port line 3. 2kbls2 keyboard line 2 level selection bit cleared to enable a low level detection on port line 2. set to enable a high level detection on port line 2. 1kbls1 keyboard line 1 level selection bit cleared to enable a low level detection on port line 1. set to enable a high level detection on port line 1. 0kbls0 keyboard line 0 level selection bit cleared to enable a low level detection on port line 0. set to enable a high level detection on port line 0.
131 at89c51re2 7663d?8051?10/08 2-wire interface (twi) this section describes the 2-wire interface. the 2-wire bus is a bi-directional 2-wire serial communication standard. it is designed primarily for simple but efficient integrated circuit (ic) control. the system is compri sed of two lines, scl (serial clock) and sda (serial data) that carry information between the ics connected to them. the serial data transfer is limited to 400 kbit/s in standard mode. various communication configuration can be designed using this bus. figure 49 shows a typical 2-wire bus configuration. all the devices connected to the bus can be master and slave. figure 49. 2-wire bus configuration scl sda device2 device1 devicen device3 ...
132 at89c51re2 7663d?8051?10/08 figure 50. block diagram address register comparator timing & control logic arbitration & sink logic serial clock generator shift register control register status register status decoder input filter output stage input filter output stage ack status bits 8 8 7 8 internal bus timer 1 overflow f clk periph /4 interrupt sda scl ssadr sscon ssdat sscs pi2.1 pi2.0
133 at89c51re2 7663d?8051?10/08 description the cpu interfaces to the 2-wire logic via the following four 8-bit special function regis- ters: the synchronous serial control register (sscon; table 107), the synchronous serial data register (ssdat; table 108), the synchronous serial control and status register (sscs; table 109) and the synchronous serial address register (ssadr table 112). sscon is used to enable the twi interface, to program the bit rate (see table 100), to enable slave modes, to acknowledge or not a received data, to send a start or a stop condition on the 2-wire bus, and to acknowledge a serial interrupt. a hardware reset disables the twi module. sscs contains a status code which reflects the status of the 2-wire logic and the 2-wire bus. the three least significant bits are always zero. the five most significant bits con- tains the status code. there are 26 possibl e status codes. when sscs contains f8h, no relevant state information is available and no serial interrupt is requested. a valid sta- tus code is available in sscs one machine cycle after si is set by hardware and is still present one machine cycle after si has been reset by software. to table 106. give the status for the master modes and miscellaneous states. ssdat contains a byte of serial data to be transmitted or a byte which has just been received. it is addressable while it is not in process of shifting a byte. this occurs when 2-wire logic is in a defined state and the serial interrupt flag is set. data in ssdat remains stable as long as si is set. while data is being shifted out, data on the bus is simultaneously shifted in; ssdat always contains the last byte present on the bus. ssadr may be loaded with the 7-bit slave address (7 most significant bits) to which the twi module will respond when programmed as a slave transmitter or receiver. the lsb is used to enable general call address (00h) recognition. figure 51 shows how a data transfer is accomplished on the 2-wire bus. figure 51. complete data transfer on 2-wire bus the four operating modes are: ? master transmitter ? master receiver ? slave transmitter ?slave receiver data transfer in each mode of operation is shown in table to table 106 and figure 52. to figure 55.. these figures contain the following abbreviations: s : start condition r : read bit (high level at sda) sda scl s start condition msb 12 7 89 ack acknowledgement signal from receiver acknowledgement signal from receiver 12 3-8 9 ack stop condition p clock line held low while interrupts are serviced
134 at89c51re2 7663d?8051?10/08 w: write bit (low level at sda) a: acknowledge bit (low level at sda) a : not acknowledge bit (high level at sda) data: 8-bit data byte p : stop condition in figure 52 to figure 55, circles are used to indicate when the serial interrupt flag is set. the numbers in the circles show the status code held in sscs. at these points, a ser- vice routine must be executed to continue or complete the serial transfer. these service routines are not critical since the serial transfer is suspended until the serial interrupt flag is cleared by software. when the serial interrupt routine is entered, the status code in sscs is used to branch to the appropriate service routine. for each status code, the required software action and details of the following serial transfer are given in table to table 106. master transmitter mode in the master transmitter mode, a number of data bytes are transmitted to a slave receiver (figure 52). before the master transmitter mode can be entered, sscon must be initialised as follows: cr0, cr1 and cr2 define the internal serial bit rate if external bit rate generator is not used. ssie must be set to enable twi. sta, sto and si must be cleared. the master transmitter mode may now be entered by setting the sta bit. the 2-wire logic will now test the 2-wire bus and gener ate a start condition as soon as the bus becomes free. when a start condition is transmitted, the serial interrupt flag (si bit in sscon) is set, and the status code in sscs will be 08h. this status must be used to vector to an interrupt routine that loads ssdat with the slave address and the data direction bit (sla+w). when the slave address and the direction bit have been transmitted and an acknowl- edgement bit has been received, si is set again and a number of status code in sscs are possible. there are 18h, 20h or 38h for the master mode and also 68h, 78h or b0h if the slave mode was enabled (aa=logic 1). the appropriate action to be taken for each of these status code is detailed in table . this scheme is repeated until a stop condi- tion is transmitted. ssie, cr2, cr1 and cr0 are not affected by the serial transfer and are referred to table 7 to table 11. after a repeated start condition (state 10h) the twi module may switch to the master receiver mode by loading ssdat with sla+r. master receiver mode in the master receiver mode, a number of data bytes are received from a slave transmit- ter (figure 53). the transfer is initialized as in the master transmitter mode. when the start condition has been transmitted, the interrupt routine must load ssdat with the 7-bit slave address and the data direction bit (sla+r). the serial interrupt flag si must then be cleared before the serial transfer can continue. table 98. sscon initialization cr2 ssie sta sto si aa cr1 cr0 bit rate 1 0 0 0 x bit rate bit rate
135 at89c51re2 7663d?8051?10/08 when the slave address and the direction bit have been transmitted and an acknowl- edgement bit has been received, the serial interrupt flag is set again and a number of status code in sscs are possible. there are 40h, 48h or 38h for the master mode and also 68h, 78h or b0h if the slave mode was enabled (aa=logic 1). the appropriate action to be taken for each of these status code is detailed in table . this scheme is repeated until a stop condition is transmitted. ssie, cr2, cr1 and cr0 are not affected by the serial transfer and are referred to table 7 to table 11. after a repeated start condition (state 10h) the twi module may switch to the master transmitter mode by loading ssdat with sla+w. slave receiver mode in the slave receiver mode, a number of data bytes are received from a master transmit- ter (figure 54). to initiate the slave receiver mode, ssadr and sscon must be loaded as follows: the upper 7 bits are the address to which the twi module will respond when addressed by a master. if the lsb (gc) is set the twi module will respond to the general call address (00h); otherwise it ignores the general call address. cr0, cr1 and cr2 have no effect in the slave mode. ssie must be set to enable the twi. the aa bit must be set to enable the own slave address or the general call address acknowledgement. sta, sto and si must be cleared. when ssadr and sscon have been initialised, the twi module waits until it is addressed by its own slave address followed by the data direction bit which must be at logic 0 (w) for the twi to operate in the slave receiver mode. after its own slave address and the w bit have been received, the serial interrupt flag is set and a valid sta- tus code can be read from sscs. this status code is used to vector to an interrupt service routine.the appropriate action to be taken for each of these status code is detailed in table . the slave receiver mode may also be entered if arbitration is lost while twi is in the master mode (states 68h and 78h). if the aa bit is reset during a transfer, twi module will return a not acknowledge (logic 1) to sda after the next received data byte. while aa is reset, the twi module does not respond to its own slave address. however, the 2-wire bus is still monitored and address recognition may be resume at any time by setting aa. this means that the aa bit may be used to temporarily isolate the module from the 2-wire bus. slave transmitter mode in the slave transmitter mode, a number of data bytes are transmitted to a master receiver (figure 55). data transfer is initia lized as in the slave receiver mode. when ssadr and sscon have been initialized, the twi module waits until it is addressed by table 99. ssadr: slave receiver mode initialization a6 a5 a4 a3 a2 a1 a0 gc own slave address table 100. sscon: slave receiver mode initialization cr2 ssie sta sto si aa cr1 cr0 bit rate 1 0 0 0 1 bit rate bit rate
136 at89c51re2 7663d?8051?10/08 its own slave address followed by the data direction bit which must be at logic 1 (r) for twi to operate in the slave transmitter mode. after its own slave address and the r bit have been received, the serial interrupt flag is set and a valid status code can be read from sscs. this status code is used to vector to an interrupt service routine. the appro- priate action to be taken for each of these st atus code is detailed in table . the slave transmitter mode may also be entered if arbitration is lost while the twi module is in the master mode. if the aa bit is reset during a transfer, the tw i module will transmit the last byte of the transfer and enter state c0h or c8h. the twi module is switched to the not addressed slave mode and will ignore the master receiver if it continues the transfer. thus the mas- ter receiver receives all 1?s as serial data. while aa is reset, the twi module does not respond to its own slave address. however, the 2-wire bus is still monitored and address recognition may be resume at any time by setting aa. this means that the aa bit may be used to temporarily isolate the twi module from the 2-wire bus. miscellaneous states there are two sscs codes that do not correspond to a define twi hardware state (table 106 ). these codes are discuss hereafter. status f8h indicates that no relevant information is available because the serial interrupt flag is not set yet. this occurs between other states and when the twi module is not involved in a serial transfer. status 00h indicates that a bus error has occurred during a twi serial transfer. a bus error is caused when a start or a stop condition occurs at an illegal position in the format frame. examples of such illegal positions happen during the serial transfer of an address byte, a data byte, or an acknowledge bit. when a bus error occurs, si is set. to recover from a bus error, the sto flag must be set and si must be cleared. this causes the twi module to enter the not addressed slave mode and to clear the sto flag (no other bits in sscon are affected). the sda and scl lines are released and no stop condition is transmitted. notes the twi module interfaces to the external 2-wire bus via two port pins: scl (serial clock line) and sda (serial data line). to avoid low level asserting on these lines when the twi module is enabled, the output latches of sda and slc must be set to logic 1. table 101. bit frequency configuration bit frequency ( khz) cr2 cr1 cr0 f osca = 12 mhz f osca = 16 mhz f osca divided by 0 0 0 47 62.5 256 0 0 1 53.5 71.5 224 0 1 0 62.5 83 192 0 1 1 75 100 160 1 0 0 - - unused 1 0 1 100 133.3 120 1 1 0 200 266.6 60 1 1 1 0.5 <. < 62.5 0.67 <. < 83 96 (256 - reload valuetimer 1) (reload value range: 0-254 in mode 2)
137 at89c51re2 7663d?8051?10/08 figure 52. format and state in the master transmitter mode sslawa data ap 08h 18h 28h mt sslaw ap ap r mr 10h 20h 30h a or a continues 38h 38h a continues 68h other master other master 78h b0h to corresponding states in slave mode successfull transmission to a slave receiver next transfer started with a repeated start condition not acknowledge received after the slave address not acknowledge received after a data arbitration lost in slave address or data byte arbitration lost and addressed as slave byte a or a continues other master data a n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in sscs) corresponds to a defined state of the 2-wire bus
138 at89c51re2 7663d?8051?10/08 table 102. status in master transmitter mode status code sssta status of the two- wire bus and two- wire hardware application software response next action taken by two-wire hardware to/from ssdat to sscon sssta sssto ssi ssaa 08h a start condition has been transmitted write sla+w x 0 0 x sla+w will be transmitted. 10h a repeated start condition has been transmitted write sla+w write sla+r x x 0 0 0 0 x x sla+w will be transmitted. sla+r will be transmitted. logic will switch to master receiver mode 18h sla+w has been transmitted; ack has been received write data byte no ssdat action no ssdat action no ssdat action 0 1 0 1 0 0 1 1 0 0 0 0 x x x x data byte will be transmitted. repeated start will be transmitted. stop condition will be transmitted and sssto flag will be reset. stop condition followed by a start condition will be transmitted and sssto flag will be reset. 20h sla+w has been transmitted; not ack has been received write data byte no ssdat action no ssdat action no ssdat action 0 1 0 1 0 0 1 1 0 0 0 0 x x x x data byte will be transmitted. repeated start will be transmitted. stop condition will be transmitted and sssto flag will be reset. stop condition followed by a start condition will be transmitted and sssto flag will be reset. 28h data byte has been transmitted; ack has been received write data byte no ssdat action no ssdat action no ssdat action 0 1 0 1 0 0 1 1 0 0 0 0 x x x x data byte will be transmitted. repeated start will be transmitted. stop condition will be transmitted and sssto flag will be reset. stop condition followed by a start condition will be transmitted and sssto flag will be reset. 30h data byte has been transmitted; not ack has been received write data byte no ssdat action no ssdat action no ssdat action 0 1 0 1 0 0 1 1 0 0 0 0 x x x x data byte will be transmitted. repeated start will be transmitted. stop condition will be transmitted and sssto flag will be reset. stop condition followed by a start condition will be transmitted and sssto flag will be reset. 38h arbitration lost in sla+w or data bytes no ssdat action no ssdat action 0 1 0 0 0 0 x x two-wire bus will be released and not addressed slave mode will be entered. a start condition will be transmitted when the bus becomes free.
139 at89c51re2 7663d?8051?10/08 figure 53. format and state in the master receiver mode sslar a data 08h 40h 58h sslar ap w mt 10h 48h a or a continues 38h 38h a continues 68h other master other master 78h b0h to corresponding states in slave mode successfull transmission to a slave receiver next transfer started with a repeated start condition not acknowledge received after the slave address arbitration lost and addressed as slave a continues other master n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in sscs) corresponds to a defined state of the 2-wire bus a data p a 50h mr arbitration lost in slave address or acknowledge bit data a
140 at89c51re2 7663d?8051?10/08 table 103. status in master receiver mode status code sssta status of the two- wire bus and two- wire hardware application software response next action taken by two-wire hardware to/from ssdat to sscon sssta sssto ssi ssaa 08h a start condition has been transmitted write sla+r x 0 0 x sla+r will be transmitted. 10h a repeated start condition has been transmitted write sla+r write sla+w x x 0 0 0 0 x x sla+r will be transmitted. sla+w will be transmitted. logic will switch to master transmitter mode. 38h arbitration lost in sla+r or not ack bit no ssdat action no ssdat action 0 1 0 0 0 0 x x two-wire bus will be released and not addressed slave mode will be entered. a start condition will be transmitted when the bus becomes free. 40h sla+r has been transmitted; ack has been received no ssdat action no ssdat action 0 0 0 0 0 0 0 1 data byte will be received and not ack will be returned. data byte will be received and ack will be returned. 48h sla+r has been transmitted; not ack has been received no ssdat action no ssdat action no ssdat action 1 0 1 0 1 1 0 0 0 x x x repeated start will be transmitted. stop condition will be transmitted and sssto flag will be reset. stop condition followed by a start condition will be transmitted and sssto flag will be reset. 50h data byte has been received; ack has been returned read data byte read data byte 0 0 0 0 0 0 0 1 data byte will be received and not ack will be returned. data byte will be received and ack will be returned. 58h data byte has been received; not ack has been returned read data byte read data byte read data byte 1 0 1 0 1 1 0 0 0 x x x repeated start will be transmitted. stop condition will be transmitted and sssto flag will be reset. stop condition followed by a start condition will be transmitted and sssto flag will be reset.
141 at89c51re2 7663d?8051?10/08 figure 54. format and state in the slave receiver mode sslawa data a data p or s a p or s a general call a data a data p or s a a 60h 68h 80h 80h a0h 88h 70h 90h 90h a0h p or s a 98h a 78h data a n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in sscs) corresponds to a defined state of the 2-wire bus reception of the own slave address and one or more data bytes. all are acknowledged. last data byte received is not acknowledged. arbitration lost as master and addressed as slave reception of the general call address and one or more data bytes. last data byte received is not acknowledged. arbitration lost as master and addressed as slave by general call
142 at89c51re2 7663d?8051?10/08 table 104. status in slave receiver mode status code (sscs) status of the 2-wire bus and 2-wire hardware application software response next action taken by 2-wire software to/from ssdat to sscon sta sto si aa 60h own sla+w has been received; ack has been returned no ssdat action or no ssdat action x x 0 0 0 0 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 68h arbitration lost in sla+r/w as master; own sla+w has been received; ack has been returned no ssdat action or no ssdat action x x 0 0 0 0 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 70h general call address has been received; ack has been returned no ssdat action or no ssdat action x x 0 0 0 0 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 78h arbitration lost in sla+r/w as master; general call address has been received; ack has been returned no ssdat action or no ssdat action x x 0 0 0 0 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 80h previously addressed with own sla+w; data has been received; ack has been returned no ssdat action or no ssdat action x x 0 0 0 0 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 88h previously addressed with own sla+w; data has been received; not ack has been returned read data byte or read data byte or read data byte or read data byte 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognised; gca will be recognised if gc=logic 1 switched to the not addressed slave mode; no recognition of own sla or gca. a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognised; gca will be recognised if gc=logic 1. a start condition will be transmitted when the bus becomes free 90h previously addressed with general call; data has been received; ack has been returned read data byte or read data byte x x 0 0 0 0 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned
143 at89c51re2 7663d?8051?10/08 98h previously addressed with general call; data has been received; not ack has been returned read data byte or read data byte or read data byte or read data byte 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognised; gca will be recognised if gc=logic 1 switched to the not addressed slave mode; no recognition of own sla or gca. a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognised; gca will be recognised if gc=logic 1. a start condition will be transmitted when the bus becomes free a0h a stop condition or repeated start condition has been received while still addressed as slave no ssdat action or no ssdat action or no ssdat action or no ssdat action 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognised; gca will be recognised if gc=logic 1 switched to the not addressed slave mode; no recognition of own sla or gca. a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognised; gca will be recognised if gc=logic 1. a start condition will be transmitted when the bus becomes free table 104. status in slave receiver mode (continued) status code (sscs) status of the 2-wire bus and 2-wire hardware application software response next action taken by 2-wire software to/from ssdat to sscon sta sto si aa
144 at89c51re2 7663d?8051?10/08 figure 55. format and state in the slave transmitter mode sslar a data a data p or s a a8h b8h c0h p or s a c8h all 1?s a b0h data a n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in sscs) corresponds to a defined state of the 2-wire bus reception of the own slave address and one or more data bytes arbitration lost as master and addressed as slave last data byte transmitted. switched to not addressed slave (aa=0) table 105. status in slave transmitter mode status code (sscs) status of the 2-wire bus and 2-wire hardware application software response next action taken by 2-wire software to/from ssdat to sscon sta sto si aa a8h own sla+r has been received; ack has been returned load data byte or load data byte x x 0 0 0 0 0 1 last data byte will be transmitted and not ack will be received data byte will be transmitted and ack will be received b0h arbitration lost in sla+r/w as master; own sla+r has been received; ack has been returned load data byte or load data byte x x 0 0 0 0 0 1 last data byte will be transmitted and not ack will be received data byte will be transmitted and ack will be received b8h data byte in ssdat has been transmitted; not ack has been received load data byte or load data byte x x 0 0 0 0 0 1 last data byte will be transmitted and not ack will be received data byte will be transmitted and ack will be received
145 at89c51re2 7663d?8051?10/08 table 106. miscellaneous status c0h data byte in ssdat has been transmitted; not ack has been received no ssdat action or no ssdat action or no ssdat action or no ssdat action 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognised; gca will be recognised if gc=logic 1 switched to the not addressed slave mode; no recognition of own sla or gca. a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognised; gca will be recognised if gc=logic 1. a start condition will be transmitted when the bus becomes free c8h last data byte in ssdat has been transmitted (aa=0); ack has been received no ssdat action or no ssdat action or no ssdat action or no ssdat action 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognised; gca will be recognised if gc=logic 1 switched to the not addressed slave mode; no recognition of own sla or gca. a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognised; gca will be recognised if gc=logic 1. a start condition will be transmitted when the bus becomes free table 105. status in slave transmitter mode (continued) status code (sscs) status of the 2-wire bus and 2-wire hardware application software response next action taken by 2-wire software to/from ssdat to sscon sta sto si aa status code (sscs) status of the 2-wire bus and 2-wire hardware application software response next action taken by 2-wire software to/from ssdat to sscon sta sto si aa f8h no relevant state information available; si= 0 no ssdat action no sscon action wait or proceed current transfer 00h bus error due to an illegal start or stop condition no ssdat action 010x only the internal hardware is affected, no stop condition is sent on the bus. in all cases, the bus is released and sto is reset.
146 at89c51re2 7663d?8051?10/08 registers table 107. sscon register sscon - synchronous serial control register (93h) 76543210 cr2 ssie sta sto si aa cr1 cr0 bit number bit mnemonic description 7cr2 control rate bit 2 see table 101. 6ssie synchronous serial interface enable bit clear to disable the twi module. set to enable the twi module. 5sta start flag set to send a start condition on the bus. 4st0 stop flag set to send a stop condition on the bus. 3si synchronous serial interrupt flag set by hardware when a serial interrupt is requested. must be cleared by software to acknowledge interrupt. 2aa assert acknowledge flag clear in master and slave receiver modes, to force a not acknowledge (high level on sda). clear to disable sla or gca recognition. set to recognise sla or gca (if gc set) for entering slave receiver or transmitter modes. set in master and slave receiver modes, to force an acknowledge (low level on sda). this bit has no effect when in master transmitter mode. 1cr1 control rate bit 1 see table 101. 0cr0 control rate bit 0 see table 101. table 108. ssdat (95h) - syncrhonous serial data register (read/write) sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 76543210 bit number bit mnemonic description 7 sd7 address bit 7 or data bit 7. 6 sd6 address bit 6 or data bit 6. 5 sd5 address bit 5 or data bit 5. 4 sd4 address bit 4 or data bit 4. 3 sd3 address bit 3 or data bit 3. 2 sd2 address bit 2 or data bit 2.
147 at89c51re2 7663d?8051?10/08 table 111. ssadr (096h) - synchronus serial address register (read/write) table 112. ssadr register - reset value = feh 1 sd1 address bit 1 or data bit 1. 0 sd0 address bit 0 (r/w) or data bit 0. table 109. sscs (094h) read - synchronous serial control and status register 76543210 sc4 sc3 sc2 sc1 sc0 0 0 0 table 110. sscs register: read mode - reset value = f8h bit number bit mnemonic description 0 0 always zero 1 0 always zero 2 0 always zero 3sc0 status code bit 0 see to table 106. 4sc1 status code bit 1 see to table 106. 5sc2 status code bit 2 see to table 106. 6sc3 status code bit 3 see to table 106. 7sc4 status code bit 4 see to table 106. 76543210 a7 a6 a5 a4 a3 a2 a1 a0 bit number bit mnemonic description 7 a7 slave address bit 7 6 a6 slave address bit 6 5 a5 slave address bit 5 4 a4 slave address bit 4 3 a3 slave address bit 3 2 a2 slave address bit 2 1 a1 slave address bit 1 bit number bit mnemonic description
148 at89c51re2 7663d?8051?10/08 0gc general call bit clear to disable the general call address recognition. set to enable the general call address recognition. bit number bit mnemonic description
149 7663e?8051?10/08 at89c51re2 serial port interface (spi) the serial peripheral interface module (spi) allows full-duplex, synchronous, serial communica- tion between the mcu and peripheral devices, including other mcus. features features of the spi module include the following: ? full-duplex, three-wire synchronous transfers ? master or slave operation ? six programmable master clock rates in master mode ? serial clock with programmable polarity and phase ? master mode fault error flag with mcu interrupt capability signal description figure 56 shows a typical spi bus configuration using one master controller and many slave peripherals. the bus is made of three wires connecting all the devices. figure 56. spi master/slaves interconnection the master device selects the individual slave devices by using four pins of a parallel port to control the four ss pins of the slave devices. master output slave input (mosi) this 1-bit signal is directly connected between the master device and a slave device. the mosi line is used to transfer data in series from the master to the slave. therefore, it is an output sig- nal from the master, and an input signal to a slave. a byte (8-bit word) is transmitted most significant bit (msb) first, least significant bit (lsb) last. master input slave output (miso) this 1-bit signal is directly connected between the slave device and a master device. the miso line is used to transfer data in series from the slave to the master. therefore, it is an output sig- nal from the slave, and an input signal to the master. a byte (8-bit word) is transmitted most significant bit (msb) first, least significant bit (lsb) last. spi serial clock (sck) this signal is used to synchronize the data transmission both in and out of the devices through their mosi and miso lines. it is driven by the master for eight clock cycles which allows to exchange one byte on the serial lines. slave select (ss ) each slave peripheral is selected by one slave select pin (ss ). this signal must stay low for any message for a slave. it is obvi ous that only one master (ss high level) can drive the network. the master may select each slave device by software through port pins (figure 57). to prevent bus conflicts on the miso line, only one slave should be selected at a time by the master for a transmission. slave 1 miso mosi sck ss miso mosi sck ss port 0 1 2 3 slave 3 miso mosi sck ss slave 4 miso mosi sck ss slave 2 miso mosi sck ss vdd master
150 7663e?8051?10/08 at89c51re2 in a master configuration, the ss line can be used in conjunction with the modf flag in the spi status register (spscr) to prevent multiple masters from driving mosi and sck (see error conditions). a high level on the ss pin puts the miso line of a slave spi in a high-impedance state. the ss pin could be used as a general-purpose if the following conditions are met: ? the device is configured as a master and the ssdis control bit in spcon is set. this kind of configuration can be found when only one master is driving the network and there is no way that the ss pin could be pulled low. therefore, the modf flag in the spscr will never be set (1) . ? the device is configured as a slave with cpha and ssdis control bits set (2) . this kind of configuration can happen when the system includes one master and one slave only. therefore, the device should always be selected and there is no reason that the master uses the ss pin to select the communicating slave device. note: 1. clearing ssdis control bit does not clear modf. 2. special care should be taken not to set ssdis control bit when cpha =?0? because in this mode, the ss is used to start the transmission. baud rate in master mode, the baud rate can be selected from a baud rate generator which is controlled by three bits in the spcon register: spr2, spr1 and spr0.the master clock is selected from one of seven clock rates resulting from the division of the internal clock by 4, 8, 16, 32, 64 or 128. table 113 gives the different clock rates selected by spr2:spr1:spr0. in slave mode, the maximum baud rate allowed on the sck input is limited to f sys /4 table 113. spi master baud rate selection spr2 spr1 spr0 clock rate baud rate divisor (bd) 0 0 0 don?t use no brg 001 f clk periph /4 4 010 f clk periph /8 8 011 f clk periph /16 16 100 f clk periph /32 32 101 f clk periph /64 64 110 f clk periph /128 128 1 1 1 don?t use no brg
151 7663e?8051?10/08 at89c51re2 functional description figure 57 shows a detailed structure of the spi module. figure 57. spi module block diagram operating modes the serial peripheral interface can be configur ed in one of the two modes: master mode or slave mode. the configuration and initializa tion of the spi module is made through two registers: ? the serial peripheral control register (spcon) ? the serial peripheral status and control register (spscr) once the spi is configured, the data exchange is made using: ? the serial peripheral data register (spdat) during an spi transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). a serial clock line (sck) synchronizes shifting and sampling on the two serial data lines (mosi and miso). a slave select line (ss ) allows individual selection of a slave spi device; slave devices that are not selected do not interfere with spi bus activities. shift register 0 1 2 3 4 5 6 7 internal bus pin control logic miso mosi sck m s clock logic spi interrupt 8-bit bus 1-bit signal ss fclk receive data register spdat spi control transmit data register -modf spif ovr spte uartm spteie modfie spscr spen mstr spr2 ssdis cpol cpha spr1 spr0 spcon request periph
152 7663e?8051?10/08 at89c51re2 when the master device transmits data to the slave device via the mosi line, the slave device responds by sending data to the master device via the miso line. this implies full-duplex trans- mission with both data out and data in synchronized with the same clock (figure 58). figure 58. full-duplex master-slave interconnection master mode the spi operates in master mode when the master bit, mstr (1) , in the spcon register is set. only one master spi device can initiate transmissions. software begins the transmission from a master spi module by writing to the serial peripheral data register (spdat). if the shift register is empty, the byte is immediately transferred to the shift register. the byte begins shifting out on mosi pin under the control of the serial clock, sck. simultaneously, another byte shifts in from the slave on the master?s miso pin. the transmission ends when the serial peripheral transfer data flag, spif, in spscr becomes set. at the same time that spif becomes set, the received byte from the slave is transferred to the receive data register in spdat. software clears spif by reading the serial peripheral status register (spscr) with the spif bit set, and then reading the spdat. slave mode the spi operates in slave mode when the master bit, mstr (2) , in the spcon register is cleared. before a data transmission occurs, the slave select pin, ss , of the slave device must be set to?0?. ss must remain low until the transmission is complete. in a slave spi module, data enters the shift register under the control of the sck from the mas- ter spi module. after a byte enters the shift register, it is immediately transferred to the receive data register in spdat, and the spif bit is set. to prevent an overflow condition, slave software must then read the spdat before another byte enters the shift register (3) . a slave spi must complete the write to the spdat (shift register) at least one bus cycle before the master spi starts a transmission. if the write to the data register is late, the spi transmits the data already in the shift register from the previous transmission. transmission formats software can select any of four combinations of serial clock (sck) phase and polarity using two bits in the spcon: the clock polarity (cpol (4) ) and the clock phase (cpha 4 ). cpol defines the default sck line level in idle state. it has no significant effect on the transmission format. cpha defines the edges on which the input data are sampled and the edges on which the out- put data are shifted (figure 59 and figure 60). the clock phase and polarity should be identical for the master spi device and the communicating slave device. 8-bit shift register spi clock generator master mcu 8-bit shift register miso miso mosi mosi sck sck vss vdd ss ss slave mcu 1. the spi module should be configured as a master before it is enabled (spen set). also, the mas- ter spi should be configured before the slave spi. 2. the spi module should be configured as a slave before it is enabled (spen set). 3. the maximum frequency of the sck for an spi configured as a slave is the bus clock speed. 4. before writing to the cpol and cpha bits, the spi should be disabled (spen =?0?).
153 7663e?8051?10/08 at89c51re2 figure 59. data transmission format (cpha = 0) figure 60. data transmission format (cpha = 1) figure 61. cpha/ss timing as shown in figure 59, the first sck edge is the msb capture strobe. therefore, the slave must begin driving its data before the first sck edge, and a falling edge on the ss pin is used to start the transmission. the ss pin must be toggled high and then low between each byte transmitted (figure 61). figure 60 shows an spi transmission in which cpha is?1?. in this case, the master begins driv- ing its mosi pin on the first sck edge. therefore, the slave uses the first sck edge as a start transmission signal. the ss pin can remain low between transmissions (figure 61). this format may be preferred in systems having only one master and only one slave driving the miso data line. queuing transmission for an spi configured in master or slave mode, a queued data byte must be transmit- ted/received immediately after the previous transmission has completed. msb bit6 bit5 bit4 bit3 bit2 bit1 lsb bit6 bit5 bit4 bit3 bit2 bit1 msb lsb 13 245678 capture point ss (to slave) miso (from slave) mosi (from master) sck (cpol = 1) sck (cpol = 0) spen (internal) sck cycle number msb bit6 bit5 bit4 bit3 bit2 bit1 lsb bit6 bit5 bit4 bit3 bit2 bit1 msb lsb 13 2 45678 capture point ss (to slave) miso (from slave) mosi (from master) sck (cpol = 1) sck (cpol = 0) spen (internal) sck cycle number byte 1 byte 2 byte 3 miso/mosi master ss slave ss (cpha = 1) slave ss (cpha = 0)
154 7663e?8051?10/08 at89c51re2 when a transmission is in progress a new data can be queued and sent as soon as transmission has been completed. so it is possible to transmit bytes without latency, useful in some applications. the spte bit in spscr is set as long as the transmission buffer is free. it means that the user application can write spdat with the data to be transmitted until the spte becomes cleared. figure 62 shows a queuing transmission in master mode. once the byte 1 is ready, it is immedi- ately sent on the bus. meanwhile an other byte is prepared (and the spte is cleared), it will be sent at the end of the current transmission. the next data must be ready before the end of the current transmission. figure 62. queuing transmission in master mode in slave mode it is almost the same except it is the external master that start the transmission. also, in slave mode, if no new data is ready, the last value received will be the next data byte transmitted. msb b6 b5 b4 b3 b2 b1 lsb mosi sck msb b6 b5 b4 b3 b2 b1 lsb byte 1 under transmission msb b6 b5 b4 b3 b2 b1 lsb msb b6 b5 b4 b3 b2 b1 lsb miso data byte 1 byte 2 byte 3 spte byte 2 under transmission
155 7663e?8051?10/08 at89c51re2 error conditions the following flags in the spscr register indicate the spi error conditions: mode fault error (modf) mode fault error in master mode spi indicates that the level on the slave select (ss ) pin is inconsistent with the actual mode of the device. ? mode fault detection in master mode: modf is set to warn that there may be a multi-master conflict for system control. in this case, the spi system is affected in the following ways: ? an spi receiver/error cpu interrupt request is generated ? the spen bit in spcon is cleared. this disables the spi ? the mstr bit in spcon is cleared clearing the modf bit is accomplished by a read of spscr register with modf bit set, followed by a write to the spcon register. spen control bit may be restored to its original set state after the modf bit has been cleared. figure 63. mode fault conditions in master mode (cpha =?1?/cpol =?0?) note: when ss is discarded (ss disabled) it is not possible to detect a modf error in master mode because the spi is internally unselected and the ss pin is a general purpose i/o. ? mode fault detection in slave mode in slave mode, the modf error is detected when ss goes high during a transmission. a transmission begins when ss goes low and ends once the incoming sck goes back to its idle level following the shift of the eighteen data bit. a modf error occurs if a slave is selected (ss is low) and later unselected (ss is high) even if no sck is sent to that slave. at any time, a?1? on the ss pin of a slave spi puts the miso pin in a high impedance state and internal state counter is cleared. also, the slave spi ignores all incoming sck clocks, even if it was already in the middle of a transmission. a new transmission will be performed as soon as ss pin returns low. sck ss (master) 1 2 3 sck cycle # 0 0 ss (slave) (from master) modf detected b6 msb b6 msb 0 z 1 0 z 1 0 z 1 0 z 1 0 z 1 0 0 z 1 spi enable modf detected mosi miso (from master) (from slave) b5
156 7663e?8051?10/08 at89c51re2 figure 64. mode fault conditions in slave mode note: when ss is discarded (ss disabled) it is not possible to detect a modf error in slave mode because the spi is internally selected. also the ss pin becomes a general purpose i/o. overrun condition this error mean that the speed is not adapted for the running application: an overrun condition occurs when a byte has been received whereas the previous one has not been read by the application yet. the last byte (which generate the overrun error) does not overwrite the unread data so that it can still be read. therefore, an overrun error always indicates the loss of data. interrupts three spi status flags can generate a cpu interrupt requests: table 114. spi interrupts serial peripheral data transfer flag, spif: this bit is set by hardware when a transfer has been completed. spif bit generates transmitter cpu interrupt request only when spteie is disabled. mode fault flag, modf: this bit is set to indicate that the level on the ss is inconsistent with the mode of the spi (in both master and slave modes). serial peripheral transmit register empty flag, spte: this bit is set when the transmit buffer is empty (other data can be loaded is spdat). spte bit generates transmitter cpu interrupt request only when spteie is enabled. note: while using spte interruption for ?burst mode? transfers (spteie=?1?), the user soft- ware application should take care to clear spteie, during the last but one data reception (to be able to generate an interrupt on spif flag at the end of the last data reception). sck 1 2 3 sck cycle # 0 ss (slave) (from master) modf detected b6 msb b6 msb 0 z 1 0 z 1 0 z 1 0 z 1 0 modf detected mosi miso (from master) (from slave) msb b5 b4 4 flag request spif (spi data transfer) spi transmitter interrupt request modf (mode fault) spi mode-fault interrupt request spte (transmit register empty) spi transmit register empty interrupt request
157 7663e?8051?10/08 at89c51re2 figure 65. spi interrupt requests generation registers three registers in the spi module provide control, status and data storage functions. these reg- isters are describe in the following paragraphs. serial peripheral control register (spcon) ? the serial peripheral control register does the following: ? selects one of the master clock rates ? configure the spi module as master or slave ? selects serial clock polarity and phase ? enables the spi module ? frees the ss pin for a general-purpose table 115 describes this register and explains the use of each bit table 115. spcon register spcon - serial peripheral control register (0d4h) spi cpu interrupt request spif spteie spte modf modfie 76543210 spr2 spen ssdis mstr cpol cpha spr1 spr0 bit number bit mnemonic description 7spr2 serial peripheral rate 2 bit with spr1 and spr0 define the clock rate (see bits spr1 and spr0 for detail). 6 spen serial peripheral enable cleared to disable the spi interface (internal reset of the spi). set to enable the spi interface. 5ssdis ss disable cleared to enable ss in both master and slave modes. set to disable ss in both master and slave modes. in slave mode, this bit has no effect if cpha =?0?. when ssdis is set, no modf interrupt request is generated . 4mstr serial peripheral master cleared to configure the spi as a slave. set to configure the spi as a master.
158 7663e?8051?10/08 at89c51re2 reset value = 0001 0100b not bit addressable serial peripheral status register and control (spscr) the serial peripheral status register contains flags to signal the following conditions: ? data transfer complete ? write collision ? inconsistent logic level on ss pin (mode fault error) table 116. spscr register spscr - serial peripheral status and control register (c4h) 3cpol clock polarity cleared to have the sck set to?0? in idle state. set to have the sck set to?1? in idle state. 2cpha clock phase cleared to have the data sampled when the sck leaves the idle state (see cpol). set to have the data sampled when the sck returns to idle state (see cpol). 1spr1 spr2 spr1 spr0 serial peripheral rate 0 0 0 invalid 00 1 f clk periph /4 01 0 f clk periph /8 01 1f clk periph /16 10 0f clk periph /32 10 1f clk periph /64 11 0f clk periph /128 1 1 1 invalid 0spr0 bit number bit mnemonic description 76543210 spif - ovr modf spte uartm spteie modfie bit number bit mnemonic description 7spif serial peripheral data transfer flag cleared by hardware to indicate data transfe r is in progress or has been approved by a clearing sequence. set by hardware to indicate that the data transfer has been completed. this bit is cleared when reading or writing spdata after reading spscr. 6- reserved the value read from this bit is indeterminate. do not set this bit. 5ovr overrun error flag - set by hardware when a byte is received whereas spif is set (the previous received data is not overwritten). - cleared by hardware when reading spscr
159 7663e?8051?10/08 at89c51re2 reset value = 00x0 xxxxb not bit addressable serial peripheral data register (spdat) the serial peripheral data register (table 117) is a read/write buffer for the receive data regis- ter. a write to spdat places data directly into the shift register. no transmit buffer is available in this model. a read of the spdat returns the value located in the receive buffer and not the content of the shift register. table 117. spdat register spdat - serial peripheral data register (c5h) reset value = indeterminate r7:r0: receive data bits 4modf mode fault - set by hardware to indicate that the ss pin is in inappropriate logic level (in both master and slave modes). - cleared by hardware when reading spscr when modf error occurred: - in slave mode: spi interface ignores all transmitted data while ss remains high. a new transmission is perform as soon as ss returns low. - in master mode: spi interface is disabled (spen=0, see description for spen bit in spcon register). 3 spte serial peripheral transmit register empty - set by hardware when transmit register is empty (if needed, spdat can be loaded with another data). - cleared by hardware when transmit register is full (no more data should be loaded in spdat). 2uartm serial peripheral uart mode set and cleared by software: - clear: normal mode, data are transmitted msb first (default) - set: uart mode, data are transmitted lsb first. 1spteie interrupt enable for spte set and cleared by software: - set to enable spte interrupt generation (when spte goes high, an interrupt is generated). - clear to disable spte interrupt generation caution: when spteie is set no interrupt generation occurred when spif flag goes high. to enable spif interrupt again, spteie should be cleared. 0modfie interrupt enable for modf set and cleared by software: - set to enable modf interrupt generation - clear to disable modf interrupt generation bit number bit mnemonic description 76543210 r7 r6 r5 r4 r3 r2 r1 r0
160 7663e?8051?10/08 at89c51re2 spcon, spsta and spdat registers may be read and written at any time while there is no on- going exchange. however, special care should be taken when writing to them while a transmis- sion is on-going: ? do not change spr2, spr1 and spr0 ? do not change cpha and cpol ? do not change mstr ? clearing spen would immediately disable the peripheral ? writing to the spdat will cause an overflow.
161 7663e?8051?10/08 at89c51re2 power monitor the por/pfd function monitors the internal power-supply of the cpu core memories and the peripherals, and if needed, suspends their activity when the internal power supply falls below a safety threshold. this is achieved by applying an internal reset to them. by generating the reset the power monitor insures a correct start up when at89c51re2 is powered up. description in order to startup and maintain the microcontroller in correct operating mode, v cc has to be sta- bilized in the v cc operating range and the oscillator has to be stabilized with a nominal amplitude compatible with logic level vih/vil. these parameters are controlled during the three phases: power-up, normal operation and power going down. see figure 66. figure 66. power monitor block diagram note: 1. once xtal1 high and low levels reach above and below vih/vil. a 1024 clock period delay will extend the reset coming from the power fail detect. if the power falls below the power fail detect threshold level, the reset will be applied immediately. the voltage regulator generates a regulated internal supply for the cpu core the memories and the peripherals. spikes on the external vcc are smoothed by the voltage regulator. vcc power on reset power fail detect voltage regulator xtal1 (1) cpu core memories peripherals regulated supply rst pin hardware watchdog pca watchdog internal reset
162 7663e?8051?10/08 at89c51re2 the power fail detect monitor the supply generated by the voltage regulator and generate a reset if this supply falls below a safety threshold as illustrated in the figure 67 below. figure 67. power fail detect when the power is applied, the power monitor immediately asserts a reset. once the internal supply after the voltage regulator reach a safety level, the power monitor then looks at the xtal clock input. the internal reset will remain asserted until the xtal1 levels are above and below vih and vil. further more. an internal counter will count 1024 clock periods before the reset is de-asserted. if the internal power supply falls below a safety level, a reset is immediately asserted. vcc t reset vcc
163 7663e?8051?10/08 at89c51re2 power-off flag the power-off flag allows the user to distinguish between a ?cold start? reset and a ?warm start? reset. a cold start reset is the one induced by v cc switch-on. a warm start reset occurs while v cc is still applied to the device and could be generated for example by an exit from power-down. the power-off flag (pof) is located in pcon register (table 118). pof is set by hardware when v cc rises from 0 to its nominal voltage. the pof can be set or cleared by software allowing the user to determine the type of reset. table 118. pcon register pcon - power control register (87h) reset value = 00x1 0000b not bit addressable 76543210 smod1 smod0 - pof gf1 gf0 pd idl bit number bit mnemonic description 7smod1 serial port mode bit 1 set to select double baud rate in mode 1, 2 or 3. 6smod0 serial port mode bit 0 cleared to select sm0 bit in scon register. set to select fe bit in scon register. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4pof power-off flag cleared to recognize next reset type. set by hardware when v cc rises from 0 to its nominal voltage. can also be set by software. 3gf1 general purpose flag cleared by user for general purpose usage. set by user for general purpose usage. 2gf0 general purpose flag cleared by user for general purpose usage. set by user for general purpose usage. 1pd power-down mode bit cleared by hardware when reset occurs. set to enter power-down mode. 0idl idle mode bit cleared by hardware when interrupt or reset occurs. set to enter idle mode.
164 7663e?8051?10/08 at89c51re2 reset introduction the reset sources are: power management, hardware watchdog, pca watchdog and reset input. figure 68. reset schematic reset input the reset input can be used to force a reset pu lse longer than the internal reset controlled by the power monitor. rst input has a pull-down re sistor allowing power-on reset by simply con- necting an external capacitor to v cc as shown in figure 69. resistor value and input characteristics are discussed in the section ?dc characteristics? of the at89c51re2 datasheet. figure 69. reset circuitry and power-on reset power monitor hardware watchdog pca watchdog rst internal reset rst r rst vss to internal reset rst vdd + b. power-on reset a. rst input circuitry
165 7663e?8051?10/08 at89c51re2 reset output as detailed in section ?hardware watchdog timer?, page 124, the wdt generates a 96-clock period pulse on the rst pin. in order to properly propagate this pulse to the rest of the applica- tion in case of external capacitor or power-supply supervisor circuit, a 1 k resistor must be added as shown figure 70. figure 70. recommended reset output schematic rst vdd + vss vdd rst 1k to other on-board circuitry
166 7663e?8051?10/08 at89c51re2 electrical characteristics absolute maximum ratings dc parameters i = industrial ........................................................-40 c to 85 c storage temperature .................................... -65 c to + 150 c voltage on v cc to v ss (standard voltage) .........-0.5v to + 6.5v voltage on v cc to v ss (low voltage)..................-0.5v to + 4.5v voltage on any pin to v ss ..........................-0.5v to v cc + 0.5v power dissipation ........................................................... 1 w (2) note: stresses at or above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions may affect device reliability. power dissipation is based on the maximum allow- able die temperature and the thermal resistance of the package. t a = -40 c to +85 c; v ss = 0v; v cc =2.7v to 5.5v; f = 0 to 40 mhz symbol parameter min typ max unit test conditions v il input low voltage -0.5 0.2 v cc - 0.1 v v ih input high voltage except rst, xtal1 0.2 v cc + 0.9 v cc + 0.5 v v ih1 input high voltage rst, xtal1 0.7 v cc v cc + 0.5 v v ol output low voltage, ports 1, 2, 3, 4 (6) 0.3 0.45 1.0 v v v v cc = 4.5v to 5.5v i ol = 100 a (4) i ol = 1.6 ma (4) i ol = 3.5 ma (4) 0.45 v v cc = 2.7v to 5.5v i ol = 0.8 ma (4) v ol1 output low voltage, port 0, ale, psen (6) 0.3 0.45 1.0 v v v v cc = 4.5v to 5.5v i ol = 200 a (4) i ol = 3.2 ma (4) i ol = 7.0 ma (4) 0.45 v v cc = 2.7v to 5.5v i ol = 1.6 ma (4) v oh output high voltage, ports 1, 2, 3, 4 v cc - 0.3 v cc - 0.7 v cc - 1.5 v v v v cc = 5v 10% i oh = -10 a i oh = -30 a i oh = -60 a 0.9 v cc v v cc = 2.7v to 5.5v i oh = -10 a v oh1 output high voltage, port 0, ale, psen v cc - 0.3 v cc - 0.7 v cc - 1.5 v v v v cc = 5v 10% i oh = -200 a i oh = -3.2 ma i oh = -7.0 ma 0.9 v cc v v cc = 2.7v to 5.5v i oh = -10 a
167 7663e?8051?10/08 at89c51re2 notes: 1. operating i cc is measured with all output pins disconnected; xtal1 driven with t clch , t chcl = 5 ns (see figure 74), v il = v ss + 0.5v, v ih = v cc - 0.5v; xtal2 n.c.; ea = rst = port 0 = v cc . i cc would be slightly higher if a crystal oscillator used (see figure 71). 2. idle i cc is measured with all output pins disconnected; xtal1 driven with t clch , t chcl = 5 ns, v il = v ss + 0.5v, v ih = v cc - 0.5v; xtal2 n.c; port 0 = v cc ; ea = rst = v ss (see figure 72). 3. power-down i cc is measured with all output pins disconnected; ea = v cc , port 0 = v cc ; xtal2 nc.; rst = v ss (see fig- ure 73). 4. capacitance loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the v ols of ale and ports 1 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1 to 0 transitions during bus operation. in the worst cases (capacitive loading 100 pf), the noise pulse on the ale line may exceed 0.45v with maxi v ol peak 0.6v. a schmitt trigger use is not necessary. 5. typical values are based on a limited number of samples and are not guaranteed. the values listed are at room temperature and 5v. 6. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 10 ma maximum i ol per 8-bit port: port 0: 26 ma ports 1, 2 and 3: 15 ma maximum total i ol for all output pins: 71 ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. figure 71. i cc test condition, active mode r rst rst pull-down resistor 50 200 (5) 250 k i il logical 0 input current ports 1, 2, 3, 4 and 5 -50 av in = 0.45v i li input leakage current 10 a 0.45v < v in < v cc i tl logical 1 to 0 transition current, ports 1, 2, 3, 4 -650 av in = 2.0v c io capacitance of i/o buffer 10 pf f c = 3 mhz t a = 25 c i pd power-down current 75 150 a2.7 < v cc < 5.5v (3) i ccop power supply current on normal mode 0.4 x frequency (mhz) + 5 ma v cc = 5.5v (1) i ccidle power supply current on idle mode 0.3 x frequency (mhz) + 5 ma v cc = 5.5v (2) i ccwrite power supply current on flash write 0.8 x frequency (mhz) + 15 ma v cc = 5.5v t write flash programming time 7 10 ms 2.7 < v cc < 5.5v t a = -40 c to +85 c; v ss = 0v; v cc =2.7v to 5.5v; f = 0 to 40 mhz (continued) symbol parameter min typ max unit test conditions ea v cc v cc i cc (nc) clock signal v cc all other pins are disconnected. rst xtal2 xtal1 v ss v cc p0
168 7663e?8051?10/08 at89c51re2 figure 72. i cc test condition, idle mode figure 73. i cc test condition, power-down mode figure 74. clock signal waveform for i cc tests in active and idle modes ac parameters explanation of the ac symbols each timing symbol has 5 characters. the first character is always a ?t? (stands for time). the other characters, depending on their positions, stand for the name of a signal or the logical sta- tus of that signal. the following is a list of all the characters and what they stand for. example:t avll = time for address valid to ale low. t llpl = time for ale low to psen low. (load capacitance for port 0, ale and psen = 100 pf; load capacitance for all other outputs = 80 pf.) table 119 table 122, and table 125 give the description of each ac symbols. table 120, table 121, table 123 and table 126 gives the range for each ac parameter. table 120, table 121 and table 127 give the frequency derating formula of the ac parameter for each speed range description. to calculate each ac symbols. take the x value in the corre- sponding column (-m or -l) and use this value in the formula. rst ea xtal2 xtal1 v ss v cc v cc i cc (nc) p0 v cc all other pins are disconnected. clock signal rst ea xtal2 xtal1 v ss v cc v cc i cc (nc) p0 v cc all other pins are disconnected. v cc -0.5v 0.45v 0.7v cc 0.2v cc -0.1 t clch t chcl t clch = t chcl = 5ns.
169 7663e?8051?10/08 at89c51re2 example: t lliu for -m and 20 mhz, standard clock. x = 35 ns t 50 ns t cciv = 4t - x = 165 ns external program memory characteristics table 119. symbol description table 120. ac parameters for a fix clock notes: 1. ? -l ? refers to 2v - 5.5v version. 2. ? -m ? refers to 4.5v to 5.5v version. symbol parameter t oscillator clock period t lhll ale pulse width t avll address valid to ale t llax address hold after ale t lliv ale to valid instruction in t llpl ale to psen t plph psen pulse width t pliv psen to valid instruction in t pxix input instruction hold after psen t pxiz input instruction float after psen t aviv address to valid instruction in t plaz psen low to address float symbol -m (1) -l (2) units min max min max t25 25 ns t lhll 35 35 ns t avll 55ns t llax 55ns t lliv n 65 65 ns t llpl 55ns t plph 50 50 ns t pliv 30 30 ns t pxix 00ns t pxiz 10 10 ns t aviv 80 80 ns t plaz 10 10 ns
170 7663e?8051?10/08 at89c51re2 table 121. ac parameters for a variable clock notes: 1. ? -l ? refers to 2v - 5.5v version. 2. ? -m ? refers to 4.5v to 5.5v version. symbol type standard clock x2 clock x parameter for -m (1) range x parameter for -l (2) range units t lhll min 2 t - x t - x 15 15 ns t avll min t - x 0.5 t - x 20 20 ns t llax min t - x 0.5 t - x 20 20 ns t lliv max 4 t - x 2 t - x 35 35 ns t llpl min t - x 0.5 t - x 15 15 ns t plph min 3 t - x 1.5 t - x 25 25 ns t pliv max 3 t - x 1.5 t - x 45 45 ns t pxix min x x 0 0 ns t pxiz max t - x 0.5 t - x 15 15 ns t aviv max 5 t - x 2.5 t - x 45 45 ns t plaz max x x 10 10 ns
171 7663e?8051?10/08 at89c51re2 external program memory read cycle external data memory characteristics table 122. symbol description t pliv tplaz ale psen port 0 port 2 a0-a7 a0-a7 instr in instr in instr in address or sfr-p2 address a8-a15 address a8-a15 12 t clcl t aviv t lhll t avll t lliv t llpl t plph t pxav t pxix t pxiz t llax symbol parameter t rlrh rd pulse width t wlwh wr pulse width t rldv rd to valid data in t rhdx data hold after rd t rhdz data float after rd t lldv ale to valid data in t avdv address to valid data in t llwl ale to wr or rd t avwl address to wr or rd t qvwx data valid to wr transition t qvwh data set-up to wr high t whqx data hold after wr t rlaz rd low to address float t whlh rd or wr high to ale high
172 7663e?8051?10/08 at89c51re2 table 123. ac parameters for a fix clock notes: 1. ? -l ? refers to 2v - 5.5v version. 2. ? -m ? refers to 4.5v to 5.5v version. symbol -m (1) -l (2) units min max min max t rlrh 125 125 ns t wlwh 125 125 ns t rldv 95 95 ns t rhdx 00ns t rhdz 25 25 ns t lldv 155 155 ns t avdv 160 160 ns t llwl 45 105 45 105 ns t av wl 70 70 ns t qvwx 55ns t qvwh 155 155 ns t whqx 10 10 ns t rlaz 00ns t whlh 5 45 5 45 ns
173 7663e?8051?10/08 at89c51re2 notes: 1. ? -l ? refers to 2v - 5.5v version. 2. ? -m ? refers to 4.5v to 5.5v version. external data memory write cycle table 124. ac parameters for a variable clock symbol type standard clock x2 clock x parameter for -m (1) range x parameter for -l (2) range units t rlrh min 6 t - x 3 t - x 25 25 ns t wlwh min 6 t - x 3 t - x 25 25 ns t rldv max 5 t - x 2.5 t - x 30 30 ns t rhdx min x x 0 0 ns t rhdz max 2 t - x t - x 25 25 ns t lldv max 8 t - x 4t -x 45 45 ns t av dv max 9 t - x 4.5 t - x 65 65 ns t llwl min 3 t - x 1.5 t - x 30 30 ns t llwl max 3 t + x 1.5 t + x 30 30 ns t avwl min 4 t - x 2 t - x 30 30 ns t qvwx min t - x 0.5 t - x 20 20 ns t qvwh min 7 t - x 3.5 t - x 20 20 ns t whqx min t - x 0.5 t - x 15 15 ns t rlaz max x x 0 0 ns t whlh min t - x 0.5 t - x 20 20 ns t whlh max t + x 0.5 t + x 20 20 ns t qvwh t llax ale psen wr port 0 port 2 a0-a7 data out address or sfr-p2 t avwl t llwl t qvwx address a8-a15 or sfr p2 t whqx t whlh t wlwh
174 7663e?8051?10/08 at89c51re2 external data memory read cycle serial port timing - shift register mode table 125. symbol description table 126. ac parameters for a fix clock notes: 1. ? -l ? refers to 2v - 5.5v version. 2. ? -m ? refers to 4.5v to 5.5v version. ale psen rd port 0 port 2 a0-a7 data in address or sfr-p2 t avwl t llwl t rlaz address a8-a15 or sfr p2 t rhdz t whlh t rlrh t lldv t rhdx t llax t avdv symbol parameter t xlxl serial port clock cycle time t qvhx output data set-up to clock rising edge t xhqx output data hold after clock rising edge t xhdx input data hold after clock rising edge t xhdv clock rising edge to input data valid symbol -m (1) -l (2) units min max min max t xlxl 300 300 ns t qvhx 200 200 ns t xhqx 30 30 ns t xhdx 00ns t xhdv 117 117 ns
175 7663e?8051?10/08 at89c51re2 table 127. ac parameters for a variable clock notes: 1. ? -l ? refers to 2v - 5.5v version. 2. ? -m ? refers to 4.5v to 5.5v version. shift register timing waveforms external clock drive waveforms ac testing input/output waveforms ac inputs during testing are driven at v cc - 0.5 for a logic ?1? and 0.45v for a logic ?0?. timing measurement are made at v ih min. for a logic ?1? and v il max for a logic ?0?. float waveforms symbol type standard clock x2 clock x parameter for -m (1) range x parameter for -l (2) range units t xlxl min 12 t 6 t ns t qvhx min 10 t - x 5 t - x 50 50 ns t xhqx min 2 t - x t - x 20 20 ns t xhdx min x x 0 0 ns t xhdv max 10 t - x 5 t- x 133 133 ns input data valid valid valid valid 0123456 8 7 ale clock output data write to sbuf clear ri t xlxl t qvxh t xhqx t xhdv t xhdx set ti set ri instruction 01234567 valid valid valid valid v cc -0.5v 0.45v 0.7v cc 0.2v cc -0.1 t chcl t clcx t clcl t clch t chcx input/output 0.2 v cc + 0.9 0.2 v cc - 0.1 v cc -0.5v 0.45v float v oh - 0.1v v ol + 0.1v v load v load + 0.1v v load - 0.1v
176 7663e?8051?10/08 at89c51re2 for timing purposes as port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loaded v oh /v ol level occurs. i ol /i oh 20 ma. clock waveforms valid in normal clock mode. in x2 mode xtal2 must be changed to xtal2/2. figure 75. internal clock signals this diagram indicates when signals are clocked internally. the time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. this propagation delay is dependent on variables such as temperature and pin loading. propaga- tion also varies from output to output and component. typically though (t a = 25 c fully loaded) rd and wr propagation delays are approximately 50 ns. the other signals are typica lly 85 ns. propagation delays are incorporated in the ac specifications. data pcl out data pcl out data pcl out sampled sampled sampled state4 state5 state6 state1 state2 state3 state4 state5 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 float float float these signals are not activated during the execution of a movx instruction indicates address transitions external program memory fetch float data sampled dpl or rt out indicates dph or p2 sfr to pch transition pcl out (if program memory is external) pcl out (even if program memory is internal) pcl out (if program memory is external) old data new data p0 pins sampled p1, p2, p3 pins sampled p1, p2, p3 pins sampled p0 pins sampled rxd sampled internal clock xtal2 ale psen p0 p2 (ext) read cycle write cycle rd p0 p2 wr port operation mov port src mov dest p0 mov dest port (p1. p2. p3) (includes into. int1. to t1) serial port shift clock txd (mode 0) data out dpl or rt out indicates dph or p2 sfr to pch transition p0 p2 rxd sampled
177 7663e?8051?10/08 at89c51re2 flash memory table 128. timing symbol definitions table 129. memory ac timing vdd = 3v to 5.5v, ta = -40 to +85 c figure 76. flash memory ? isp waveforms figure 77. flash memory ? internal busy waveforms signals conditions s (hardware condition) psen#,ea l low rrst vvalid b fbusy flag x no longer valid symbol parameter min typ max unit t svrl input psen# valid to rst edge 50 ns t rlsx input psen# hold after rst edge 50 ns t bhbl flash internal busy (programming) time 10 ms n fcy number of flash erase/write cycles 100 000 cycles t fdr flash retention time 10 years rst t svrl psen#1 t rlsx fbusy bit t bhbl
178 7663e?8051?10/08 at89c51re2 ordering information table 130. possible order entries part number supply voltage temperature range package at89c51re2-slsum 2.7v-5.5v industrial & green plcc44 at89c51re2-rltum vqfp44 AT89C51RE2-SLSEM 2.7v-5.5v engineering samples plcc44 at89c51re2-rltem vqfp44
179 7663e?8051?10/08 at89c51re2 packaging information plcc44
180 7663e?8051?10/08 at89c51re2 st and ard no tes for plcc 1/ controlling dimensions : inches 2/ dimensioning and tolerancing per ansi y 14.5m - 1982. 3/ "d" and "e1" dimensions do not include mold flash or protusions. mold flash or protusions shall not exceed 0.20 mm (.008 inch) per side.
181 7663e?8051?10/08 at89c51re2 vqfp44
182 7663e?8051?10/08 at89c51re2 st and ard no tes for pqfp / vqfp / tqfp / dqfp 1/ controlling dimensions : inches 2/ all dimensioning and tolerancing conform to ansi y 14.5m - 1982. 3/ "d1 and e1" dimensions do not include mold protusions. mold protusions shall not exceed 0.25 mm (0.010 inch). the top package body size may be smaller than the bottom package body size by as much as 0.15 mm. 4/ datum plane "h" located at mold parting line and coincident with lead, where lead exits plastic body at bottom of parting line. 5/ datum "a" and "d" to be determined at datum plane h. 6/ dimension " f " does not include dambar protusion allowable dambar protusion shall be 0.08mm/.003" total in excess of the " f " dimension at maximum material condition . dambar cannot be located on the lower radius or the foot.
183 7663e?8051?10/08 at89c51re2 document revision history changes from 7663b to 7663c 1. modified ordering information. 2. various grammatical corections throughout document. changes from 7663c to 7663d 1. twi interface added. changes from 7663d to 7663e 1. removed 64 and 68 pins package product version. 2. minor correction on table 69 on page 102.
1 7663e?8051?10/08 at89c51re2 features ................................................................................................. 1 description ............................................................................................ 2 block diagram ...................................................................................... 3 pin configurations ............................................................................... 4 sfr mapping ......................................................................................... 7 enhanced features ............................................................................ 13 x2 feature .......................................................................................................... 13 dual data pointer register dptr ..................................................... 18 memory architecture ........................................................................................... 21 expanded ram (xram) ..................................................................... 22 registers............................................................................................................. 24 extended stack................................................................................................... 25 flash memory ..................................................................................... 27 general description ............................................................................................ 27 features.............................................................................................................. 27 flash memory organization ................................................................................ 27 on-chip flash memory....................................................................................... 28 on-chip rom bootloader ................................................................................... 31 boot process....................................................................................................... 32 access and operations descriptions.................................................................. 36 operation cross memory access ..................................................... 50 sharing instructions ........................................................................... 50 flash protection from parallel programming .................................. 52 bootloader architecture ...... .............................................................. 53 introduction ......................................................................................................... 53 bootloader description ....................................................................................... 54 isp protocol description..................................................................................... 56 protocol............................................................................................................... 57 isp commands description ................................................................................ 61 timers/counters ................................................................................. 68 timer/counter operations .................................................................................. 68 timer 0................................................................................................................ 68 timer 1................................................................................................................ 71
2 7663e?8051?10/08 at89c51re2 interrupt .............................................................................................................. 71 registers............................................................................................................. 73 timer 2 ................................................................................................. 77 auto-reload mode.............................................................................................. 77 programmable clock-output .............................................................................. 78 registers............................................................................................................. 80 programmable counter array pca ................................................... 82 pca capture mode............................................................................................. 90 16-bit software timer/ compare mode............................................................... 90 high speed output mode ................................................................................... 91 pulse width modulator mode.............................................................................. 92 pca watchdog timer ......................................................................................... 93 serial i/o port ...................................................................................... 94 framing error detection ..................................................................................... 94 automatic address recognition.......................................................................... 95 registers............................................................................................................. 97 baud rate selection for uart 0 for mode 1 and 3............................................ 98 baud rate selection for uart 1 for mode 1 and 3............................................ 99 uart registers................................................................................................ 103 interrupt system ............................................................................... 109 registers........................................................................................................... 110 interrupt sources and vector addresses.......................................................... 117 power management .......................................................................... 118 introduction ....................................................................................................... 118 idle mode .......................................................................................................... 118 power-down mode ........................................................................................... 118 registers........................................................................................................... 121 oscillator ........................................................................................... 122 registers........................................................................................................... 122 functional block diagram .................................................................................123 hardware watchdog timer .............................................................. 124 using the wdt ................................................................................................. 124 wdt during power down and idle................................................................... 125 reduced emi mode ........................................................................... 126 keyboard interface ........................................................................... 127 registers........................................................................................................... 128
3 7663e?8051?10/08 at89c51re2 2-wire interface (twi) ....................................................................... 131 description........................................................................................................ 133 notes ................................................................................................................ 136 registers........................................................................................................... 146 serial port interface (spi) ................................................................ 149 features............................................................................................................ 149 signal description............................................................................................. 149 functional description ...................................................................................... 151 power monitor ................................................................................... 161 description........................................................................................................ 161 power-off flag ................................................................................... 163 reset .................................................................................................. 164 introduction ....................................................................................................... 164 reset input ....................................................................................................... 164 reset output .....................................................................................................165 electrical characteristics ................................................................. 166 absolute maximum ratings ..............................................................................166 dc parameters .................................................................................................166 ac parameters ................................................................................................. 168 ordering information ........................................................................ 178 packaging information ..................................................................... 179 plcc44 ............................................................................................................ 179 vqfp44 ............................................................................................................ 181 document revision history ............................................................. 183 changes from 7663b to 7663c ........................................................................ 183 changes from 7663c to 7663d ........................................................................ 183 changes from 7663d to 7663e ........................................................................ 183
7663e?8051?10/08 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 atmel asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 atmel europe le krebs 8, rue jean-pierre timbaud bp 309 78054 saint-quentin-en- yvelines cedex france tel: (33) 1-30-60-70-00 fax: (33) 1-30-60-71-11 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 product contact web site www.atmel.com technical support avr@atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection with atmel products. no license, expres s or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no liability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, conseque ntial, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or comple teness of the contents of this document and reserves the rig ht to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not int ended, authorized, or warranted for use as components in applications intended to support or sustain life. ? 2008 atmel corporation. all rights reserved. atmel ? , logo and combinations thereof, and others are registered trademarks or trademarks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others.

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